wenkong_junshi/Template/HARDWARE/TIM2/tim2.c

#include "tim2.h"
#include "modbus.h"
#include "All_define.h"
void BSP_TIM2_Init(u16 T35_50us) 
{
    timer_parameter_struct timer_initpara;
    rcu_periph_clock_enable(RCU_TIMER1); /* 使能 TIMx 时钟 */
	timer_struct_para_init(&timer_initpara);

    timer_deinit(TIMER1); /* 重置 TIMx 定时器 */

    /* 初始化定时器参数 */
     timer_initpara.prescaler  = 119;
     timer_initpara.alignedmode  = TIMER_COUNTER_EDGE;
     timer_initpara.counterdirection  = TIMER_COUNTER_UP;
     timer_initpara.period  = T35_50us;
     timer_initpara.clockdivision  = TIMER_CKDIV_DIV1;
     timer_init(TIMER1, &timer_initpara);

    /* 自动重装载缓冲使能 */
    timer_auto_reload_shadow_enable(TIMER1);
    /* 使能 TIMx 定时器 */
   
	
	nvic_irq_enable(TIMER1_IRQn, 6, 0);	
	
	timer_interrupt_flag_clear (TIMER1, TIMER_INT_FLAG_UP);
	timer_interrupt_enable (TIMER1, TIMER_INT_UP);
	//timer_internal_trigger_as_external_clock_config(TIMER1, TIMER_SMCFG_TRGSEL_ITI0);
	//timer_master_slave_mode_config(TIMER1,TIMER_MASTER_SLAVE_MODE_DISABLE);
	
	 timer_enable(TIMER1);
	
 // TIM_TimeBaseInitTypeDef TIM_TimerBaseInitStructure;
 // NVIC_InitTypeDef NVIC_InitStructure;
 // RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
//TIM_TimeBaseStructInit(&TIM_TimerBaseInitStructure);
  //TIM_TimerBaseInitStructure.TIM_CounterMode = TIM_CounterMode_Up;
  //TIM_TimerBaseInitStructure.TIM_Prescaler = 35;
 // TIM_TimerBaseInitStructure.TIM_Period = 100 * T35_50us;	
 // TIM_TimerBaseInitStructure.TIM_ClockDivision = TIM_CKD_DIV1;
 // TIM_TimeBaseInit(TIM2, &TIM_TimerBaseInitStructure);
 // NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
 /// NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority =6;
 // NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
 // NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
//  NVIC_Init(&NVIC_InitStructure);
  //TIM_ClearFlag(TIM2, TIM_FLAG_Update);
  //TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);
//  TIM_InternalClockConfig(TIM2);
//  TIM_SelectMasterSlaveMode(TIM2, TIM_MasterSlaveMode_Disable);
 // TIM_Cmd(TIM2, ENABLE);
}
 void vMBPortTimersEnable(  )
{
    //TIM_SetCounter(TIM2, 0);
    //TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
    //TIM_Cmd(TIM2, ENABLE);
	timer_counter_value_config(TIMER1,0);
	timer_interrupt_flag_clear(TIMER1,TIMER_INT_FLAG_UP);
	 timer_enable(TIMER1);
}
void vMBPortTimersDisable(  )
{
    //TIM_SetCounter(TIM2, 0);
   // TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
   // TIM_Cmd(TIM2, DISABLE);
	timer_counter_value_config(TIMER1,0);
	timer_interrupt_flag_clear(TIMER1,TIMER_INT_FLAG_UP);
	timer_disable(TIMER1);
}
void prvvTIMERExpiredISR( void )
{
	UART_msg ptrmsg;
	BaseType_t xSwitchRequired1 = pdFALSE;
	  switch ( eRcvState )
    {
		case STATE_RX_INIT:
			vMBPortTimersDisable(  );
			break;
		case STATE_RX_RCV:
		//	printf("232232\r\n");	
			for(u8 i = 0;i < usRcvBufferPos;i++)
			{
				//printf("  data= 0x%x/ \n ",ptrmsg.data[i]);
				ptrmsg.data[i] =  ucRTUBuf[i];
			}
			ptrmsg.len = usRcvBufferPos;
			vMBPortTimersDisable(  );
			eRcvState = STATE_RX_IDLE; 
			xQueueSendFromISR(MB_RTU_Rx_Queue,&ptrmsg,&xSwitchRequired1);
			break;
		case STATE_RX_ERROR:
			break;
		default:
			break;
    }
	eRcvState = STATE_RX_IDLE;
	portYIELD_FROM_ISR(xSwitchRequired1);
}