system_gd32f30x.c 30 KB

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  1. /*!
  2. \file system_gd32f30x.c
  3. \brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for
  4. GD32F30x Device Series
  5. */
  6. /* Copyright (c) 2012 ARM LIMITED
  7. Copyright (c) 2023, GigaDevice Semiconductor Inc.
  8. All rights reserved.
  9. Redistribution and use in source and binary forms, with or without
  10. modification, are permitted provided that the following conditions are met:
  11. - Redistributions of source code must retain the above copyright
  12. notice, this list of conditions and the following disclaimer.
  13. - Redistributions in binary form must reproduce the above copyright
  14. notice, this list of conditions and the following disclaimer in the
  15. documentation and/or other materials provided with the distribution.
  16. - Neither the name of ARM nor the names of its contributors may be used
  17. to endorse or promote products derived from this software without
  18. specific prior written permission.
  19. *
  20. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21. AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22. IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23. ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
  24. LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25. CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26. SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27. INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28. CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29. ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30. POSSIBILITY OF SUCH DAMAGE.
  31. ---------------------------------------------------------------------------*/
  32. /* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
  33. #include "gd32f30x.h"
  34. /* system frequency define */
  35. #define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */
  36. #define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
  37. #define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */
  38. /* select a system clock by uncommenting the following line */
  39. /* use IRC8M */
  40. //#define __SYSTEM_CLOCK_IRC8M (uint32_t)(__IRC8M)
  41. //#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000)
  42. //#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000)
  43. //#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000)
  44. //#define __SYSTEM_CLOCK_120M_PLL_IRC8M (uint32_t)(120000000)
  45. /* use HXTAL(XD series CK_HXTAL = 8M, CL series CK_HXTAL = 25M) */
  46. //#define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL)
  47. //#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000)
  48. //#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000)
  49. //#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000)
  50. #define __SYSTEM_CLOCK_120M_PLL_HXTAL (uint32_t)(120000000)
  51. #define RCU_MODIFY(__delay) do{ \
  52. volatile uint32_t i; \
  53. if(0 != __delay){ \
  54. RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \
  55. for(i=0; i<__delay; i++){ \
  56. } \
  57. RCU_CFG0 |= RCU_AHB_CKSYS_DIV4; \
  58. for(i=0; i<__delay; i++){ \
  59. } \
  60. } \
  61. }while(0)
  62. #define SEL_IRC8M 0x00U
  63. #define SEL_HXTAL 0x01U
  64. #define SEL_PLL 0x02U
  65. /* set the system clock frequency and declare the system clock configuration function */
  66. #ifdef __SYSTEM_CLOCK_IRC8M
  67. uint32_t SystemCoreClock = __SYSTEM_CLOCK_IRC8M;
  68. static void system_clock_8m_irc8m(void);
  69. #elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M)
  70. uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M;
  71. static void system_clock_48m_irc8m(void);
  72. #elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
  73. uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M;
  74. static void system_clock_72m_irc8m(void);
  75. #elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M)
  76. uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M;
  77. static void system_clock_108m_irc8m(void);
  78. #elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M)
  79. uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_IRC8M;
  80. static void system_clock_120m_irc8m(void);
  81. #elif defined (__SYSTEM_CLOCK_HXTAL)
  82. uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL;
  83. static void system_clock_hxtal(void);
  84. #elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
  85. uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL;
  86. static void system_clock_48m_hxtal(void);
  87. #elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
  88. uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
  89. static void system_clock_72m_hxtal(void);
  90. #elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
  91. uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL;
  92. static void system_clock_108m_hxtal(void);
  93. #elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL)
  94. uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_HXTAL;
  95. static void system_clock_120m_hxtal(void);
  96. #endif /* __SYSTEM_CLOCK_IRC8M */
  97. /* configure the system clock */
  98. static void system_clock_config(void);
  99. /*!
  100. \brief setup the microcontroller system, initialize the system
  101. \param[in] none
  102. \param[out] none
  103. \retval none
  104. */
  105. void SystemInit (void)
  106. {
  107. /* FPU settings */
  108. #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  109. SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
  110. #endif
  111. /* reset the RCU clock configuration to the default reset state */
  112. /* Set IRC8MEN bit */
  113. RCU_CTL |= RCU_CTL_IRC8MEN;
  114. while(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
  115. }
  116. RCU_MODIFY(0x50);
  117. RCU_CFG0 &= ~RCU_CFG0_SCS;
  118. #if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
  119. /* reset HXTALEN, CKMEN and PLLEN bits */
  120. RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
  121. /* disable all interrupts */
  122. RCU_INT = 0x009f0000U;
  123. #elif defined(GD32F30X_CL)
  124. /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */
  125. RCU_CTL &= ~(RCU_CTL_PLLEN |RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
  126. /* disable all interrupts */
  127. RCU_INT = 0x00ff0000U;
  128. #endif
  129. /* reset HXTALBPS bit */
  130. RCU_CTL &= ~(RCU_CTL_HXTALBPS);
  131. /* Reset CFG0 and CFG1 registers */
  132. RCU_CFG0 = 0x00000000U;
  133. RCU_CFG1 = 0x00000000U;
  134. /* configure the system clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */
  135. system_clock_config();
  136. }
  137. /*!
  138. \brief configure the system clock
  139. \param[in] none
  140. \param[out] none
  141. \retval none
  142. */
  143. static void system_clock_config(void)
  144. {
  145. #ifdef __SYSTEM_CLOCK_IRC8M
  146. system_clock_8m_irc8m();
  147. #elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M)
  148. system_clock_48m_irc8m();
  149. #elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
  150. system_clock_72m_irc8m();
  151. #elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M)
  152. system_clock_108m_irc8m();
  153. #elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M)
  154. system_clock_120m_irc8m();
  155. #elif defined (__SYSTEM_CLOCK_HXTAL)
  156. system_clock_hxtal();
  157. #elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
  158. system_clock_48m_hxtal();
  159. #elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
  160. system_clock_72m_hxtal();
  161. #elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
  162. system_clock_108m_hxtal();
  163. #elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL)
  164. system_clock_120m_hxtal();
  165. #endif /* __SYSTEM_CLOCK_IRC8M */
  166. }
  167. #ifdef __SYSTEM_CLOCK_IRC8M
  168. /*!
  169. \brief configure the system clock to 8M by IRC8M
  170. \param[in] none
  171. \param[out] none
  172. \retval none
  173. */
  174. static void system_clock_8m_irc8m(void)
  175. {
  176. uint32_t timeout = 0U;
  177. uint32_t stab_flag = 0U;
  178. /* enable IRC8M */
  179. RCU_CTL |= RCU_CTL_IRC8MEN;
  180. /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
  181. do{
  182. timeout++;
  183. stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
  184. }
  185. while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
  186. /* if fail */
  187. if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
  188. while(1){
  189. }
  190. }
  191. /* AHB = SYSCLK */
  192. RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
  193. /* APB2 = AHB/1 */
  194. RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
  195. /* APB1 = AHB/2 */
  196. RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
  197. /* select IRC8M as system clock */
  198. RCU_CFG0 &= ~RCU_CFG0_SCS;
  199. RCU_CFG0 |= RCU_CKSYSSRC_IRC8M;
  200. /* wait until IRC8M is selected as system clock */
  201. while(0U != (RCU_CFG0 & RCU_SCSS_IRC8M)){
  202. }
  203. }
  204. #elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M)
  205. /*!
  206. \brief configure the system clock to 48M by PLL which selects IRC8M as its clock source
  207. \param[in] none
  208. \param[out] none
  209. \retval none
  210. */
  211. static void system_clock_48m_irc8m(void)
  212. {
  213. uint32_t timeout = 0U;
  214. uint32_t stab_flag = 0U;
  215. /* enable IRC8M */
  216. RCU_CTL |= RCU_CTL_IRC8MEN;
  217. /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
  218. do{
  219. timeout++;
  220. stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
  221. }
  222. while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
  223. /* if fail */
  224. if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
  225. while(1){
  226. }
  227. }
  228. /* LDO output voltage high mode */
  229. RCU_APB1EN |= RCU_APB1EN_PMUEN;
  230. PMU_CTL |= PMU_CTL_LDOVS;
  231. /* IRC8M is stable */
  232. /* AHB = SYSCLK */
  233. RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
  234. /* APB2 = AHB/1 */
  235. RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
  236. /* APB1 = AHB/2 */
  237. RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
  238. /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */
  239. RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
  240. RCU_CFG0 |= RCU_PLL_MUL12;
  241. /* enable PLL */
  242. RCU_CTL |= RCU_CTL_PLLEN;
  243. /* wait until PLL is stable */
  244. while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
  245. }
  246. /* enable the high-drive to extend the clock frequency to 120 MHz */
  247. PMU_CTL |= PMU_CTL_HDEN;
  248. while(0U == (PMU_CS & PMU_CS_HDRF)){
  249. }
  250. /* select the high-drive mode */
  251. PMU_CTL |= PMU_CTL_HDS;
  252. while(0U == (PMU_CS & PMU_CS_HDSRF)){
  253. }
  254. /* select PLL as system clock */
  255. RCU_CFG0 &= ~RCU_CFG0_SCS;
  256. RCU_CFG0 |= RCU_CKSYSSRC_PLL;
  257. /* wait until PLL is selected as system clock */
  258. while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
  259. }
  260. }
  261. #elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
  262. /*!
  263. \brief configure the system clock to 72M by PLL which selects IRC8M as its clock source
  264. \param[in] none
  265. \param[out] none
  266. \retval none
  267. */
  268. static void system_clock_72m_irc8m(void)
  269. {
  270. uint32_t timeout = 0U;
  271. uint32_t stab_flag = 0U;
  272. /* enable IRC8M */
  273. RCU_CTL |= RCU_CTL_IRC8MEN;
  274. /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
  275. do{
  276. timeout++;
  277. stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
  278. }while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
  279. /* if fail */
  280. if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
  281. while(1){
  282. }
  283. }
  284. /* LDO output voltage high mode */
  285. RCU_APB1EN |= RCU_APB1EN_PMUEN;
  286. PMU_CTL |= PMU_CTL_LDOVS;
  287. /* IRC8M is stable */
  288. /* AHB = SYSCLK */
  289. RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
  290. /* APB2 = AHB/1 */
  291. RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
  292. /* APB1 = AHB/2 */
  293. RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
  294. /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */
  295. RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
  296. RCU_CFG0 |= RCU_PLL_MUL18;
  297. /* enable PLL */
  298. RCU_CTL |= RCU_CTL_PLLEN;
  299. /* wait until PLL is stable */
  300. while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
  301. }
  302. /* enable the high-drive to extend the clock frequency to 120 MHz */
  303. PMU_CTL |= PMU_CTL_HDEN;
  304. while(0U == (PMU_CS & PMU_CS_HDRF)){
  305. }
  306. /* select the high-drive mode */
  307. PMU_CTL |= PMU_CTL_HDS;
  308. while(0U == (PMU_CS & PMU_CS_HDSRF)){
  309. }
  310. /* select PLL as system clock */
  311. RCU_CFG0 &= ~RCU_CFG0_SCS;
  312. RCU_CFG0 |= RCU_CKSYSSRC_PLL;
  313. /* wait until PLL is selected as system clock */
  314. while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
  315. }
  316. }
  317. #elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M)
  318. /*!
  319. \brief configure the system clock to 108M by PLL which selects IRC8M as its clock source
  320. \param[in] none
  321. \param[out] none
  322. \retval none
  323. */
  324. static void system_clock_108m_irc8m(void)
  325. {
  326. uint32_t timeout = 0U;
  327. uint32_t stab_flag = 0U;
  328. /* enable IRC8M */
  329. RCU_CTL |= RCU_CTL_IRC8MEN;
  330. /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
  331. do{
  332. timeout++;
  333. stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
  334. }while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
  335. /* if fail */
  336. if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
  337. while(1){
  338. }
  339. }
  340. /* LDO output voltage high mode */
  341. RCU_APB1EN |= RCU_APB1EN_PMUEN;
  342. PMU_CTL |= PMU_CTL_LDOVS;
  343. /* IRC8M is stable */
  344. /* AHB = SYSCLK */
  345. RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
  346. /* APB2 = AHB/1 */
  347. RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
  348. /* APB1 = AHB/2 */
  349. RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
  350. /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */
  351. RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
  352. RCU_CFG0 |= RCU_PLL_MUL27;
  353. /* enable PLL */
  354. RCU_CTL |= RCU_CTL_PLLEN;
  355. /* wait until PLL is stable */
  356. while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
  357. }
  358. /* enable the high-drive to extend the clock frequency to 120 MHz */
  359. PMU_CTL |= PMU_CTL_HDEN;
  360. while(0U == (PMU_CS & PMU_CS_HDRF)){
  361. }
  362. /* select the high-drive mode */
  363. PMU_CTL |= PMU_CTL_HDS;
  364. while(0U == (PMU_CS & PMU_CS_HDSRF)){
  365. }
  366. /* select PLL as system clock */
  367. RCU_CFG0 &= ~RCU_CFG0_SCS;
  368. RCU_CFG0 |= RCU_CKSYSSRC_PLL;
  369. /* wait until PLL is selected as system clock */
  370. while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
  371. }
  372. }
  373. #elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M)
  374. /*!
  375. \brief configure the system clock to 120M by PLL which selects IRC8M as its clock source
  376. \param[in] none
  377. \param[out] none
  378. \retval none
  379. */
  380. static void system_clock_120m_irc8m(void)
  381. {
  382. uint32_t timeout = 0U;
  383. uint32_t stab_flag = 0U;
  384. /* enable IRC8M */
  385. RCU_CTL |= RCU_CTL_IRC8MEN;
  386. /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
  387. do{
  388. timeout++;
  389. stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
  390. }while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
  391. /* if fail */
  392. if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
  393. while(1){
  394. }
  395. }
  396. /* LDO output voltage high mode */
  397. RCU_APB1EN |= RCU_APB1EN_PMUEN;
  398. PMU_CTL |= PMU_CTL_LDOVS;
  399. /* IRC8M is stable */
  400. /* AHB = SYSCLK */
  401. RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
  402. /* APB2 = AHB/1 */
  403. RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
  404. /* APB1 = AHB/2 */
  405. RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
  406. /* CK_PLL = (CK_IRC8M/2) * 30 = 120 MHz */
  407. RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
  408. RCU_CFG0 |= RCU_PLL_MUL30;
  409. /* enable PLL */
  410. RCU_CTL |= RCU_CTL_PLLEN;
  411. /* wait until PLL is stable */
  412. while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
  413. }
  414. /* enable the high-drive to extend the clock frequency to 120 MHz */
  415. PMU_CTL |= PMU_CTL_HDEN;
  416. while(0U == (PMU_CS & PMU_CS_HDRF)){
  417. }
  418. /* select the high-drive mode */
  419. PMU_CTL |= PMU_CTL_HDS;
  420. while(0U == (PMU_CS & PMU_CS_HDSRF)){
  421. }
  422. /* select PLL as system clock */
  423. RCU_CFG0 &= ~RCU_CFG0_SCS;
  424. RCU_CFG0 |= RCU_CKSYSSRC_PLL;
  425. /* wait until PLL is selected as system clock */
  426. while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
  427. }
  428. }
  429. #elif defined (__SYSTEM_CLOCK_HXTAL)
  430. /*!
  431. \brief configure the system clock to HXTAL
  432. \param[in] none
  433. \param[out] none
  434. \retval none
  435. */
  436. static void system_clock_hxtal(void)
  437. {
  438. uint32_t timeout = 0U;
  439. uint32_t stab_flag = 0U;
  440. /* enable HXTAL */
  441. RCU_CTL |= RCU_CTL_HXTALEN;
  442. /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
  443. do{
  444. timeout++;
  445. stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
  446. }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
  447. /* if fail */
  448. if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
  449. while(1){
  450. }
  451. }
  452. /* AHB = SYSCLK */
  453. RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
  454. /* APB2 = AHB/1 */
  455. RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
  456. /* APB1 = AHB/2 */
  457. RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
  458. /* select HXTAL as system clock */
  459. RCU_CFG0 &= ~RCU_CFG0_SCS;
  460. RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
  461. /* wait until HXTAL is selected as system clock */
  462. while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){
  463. }
  464. }
  465. #elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
  466. /*!
  467. \brief configure the system clock to 48M by PLL which selects HXTAL(8M) as its clock source
  468. \param[in] none
  469. \param[out] none
  470. \retval none
  471. */
  472. static void system_clock_48m_hxtal(void)
  473. {
  474. uint32_t timeout = 0U;
  475. uint32_t stab_flag = 0U;
  476. /* enable HXTAL */
  477. RCU_CTL |= RCU_CTL_HXTALEN;
  478. /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
  479. do{
  480. timeout++;
  481. stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
  482. }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
  483. /* if fail */
  484. if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
  485. while(1){
  486. }
  487. }
  488. RCU_APB1EN |= RCU_APB1EN_PMUEN;
  489. PMU_CTL |= PMU_CTL_LDOVS;
  490. /* HXTAL is stable */
  491. /* AHB = SYSCLK */
  492. RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
  493. /* APB2 = AHB/1 */
  494. RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
  495. /* APB1 = AHB/2 */
  496. RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
  497. #if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
  498. /* select HXTAL/2 as clock source */
  499. RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0);
  500. RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0);
  501. /* CK_PLL = (CK_HXTAL/2) * 12 = 48 MHz */
  502. RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
  503. RCU_CFG0 |= RCU_PLL_MUL12;
  504. #elif defined(GD32F30X_CL)
  505. /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */
  506. RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
  507. RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL12);
  508. /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
  509. RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
  510. RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
  511. /* enable PLL1 */
  512. RCU_CTL |= RCU_CTL_PLL1EN;
  513. /* wait till PLL1 is ready */
  514. while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
  515. }
  516. #endif /* GD32F30X_HD and GD32F30X_XD */
  517. /* enable PLL */
  518. RCU_CTL |= RCU_CTL_PLLEN;
  519. /* wait until PLL is stable */
  520. while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
  521. }
  522. /* enable the high-drive to extend the clock frequency to 120 MHz */
  523. PMU_CTL |= PMU_CTL_HDEN;
  524. while(0U == (PMU_CS & PMU_CS_HDRF)){
  525. }
  526. /* select the high-drive mode */
  527. PMU_CTL |= PMU_CTL_HDS;
  528. while(0U == (PMU_CS & PMU_CS_HDSRF)){
  529. }
  530. /* select PLL as system clock */
  531. RCU_CFG0 &= ~RCU_CFG0_SCS;
  532. RCU_CFG0 |= RCU_CKSYSSRC_PLL;
  533. /* wait until PLL is selected as system clock */
  534. while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
  535. }
  536. }
  537. #elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
  538. /*!
  539. \brief configure the system clock to 72M by PLL which selects HXTAL(8M) as its clock source
  540. \param[in] none
  541. \param[out] none
  542. \retval none
  543. */
  544. static void system_clock_72m_hxtal(void)
  545. {
  546. uint32_t timeout = 0U;
  547. uint32_t stab_flag = 0U;
  548. /* enable HXTAL */
  549. RCU_CTL |= RCU_CTL_HXTALEN;
  550. /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
  551. do{
  552. timeout++;
  553. stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
  554. }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
  555. /* if fail */
  556. if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
  557. while(1){
  558. }
  559. }
  560. RCU_APB1EN |= RCU_APB1EN_PMUEN;
  561. PMU_CTL |= PMU_CTL_LDOVS;
  562. /* HXTAL is stable */
  563. /* AHB = SYSCLK */
  564. RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
  565. /* APB2 = AHB/1 */
  566. RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
  567. /* APB1 = AHB/2 */
  568. RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
  569. #if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
  570. /* select HXTAL/2 as clock source */
  571. RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0);
  572. RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0);
  573. /* CK_PLL = (CK_HXTAL/2) * 18 = 72 MHz */
  574. RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
  575. RCU_CFG0 |= RCU_PLL_MUL18;
  576. #elif defined(GD32F30X_CL)
  577. /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */
  578. RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
  579. RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL18);
  580. /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
  581. RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
  582. RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
  583. /* enable PLL1 */
  584. RCU_CTL |= RCU_CTL_PLL1EN;
  585. /* wait till PLL1 is ready */
  586. while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
  587. }
  588. #endif /* GD32F30X_HD and GD32F30X_XD */
  589. /* enable PLL */
  590. RCU_CTL |= RCU_CTL_PLLEN;
  591. /* wait until PLL is stable */
  592. while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
  593. }
  594. /* enable the high-drive to extend the clock frequency to 120 MHz */
  595. PMU_CTL |= PMU_CTL_HDEN;
  596. while(0U == (PMU_CS & PMU_CS_HDRF)){
  597. }
  598. /* select the high-drive mode */
  599. PMU_CTL |= PMU_CTL_HDS;
  600. while(0U == (PMU_CS & PMU_CS_HDSRF)){
  601. }
  602. /* select PLL as system clock */
  603. RCU_CFG0 &= ~RCU_CFG0_SCS;
  604. RCU_CFG0 |= RCU_CKSYSSRC_PLL;
  605. /* wait until PLL is selected as system clock */
  606. while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
  607. }
  608. }
  609. #elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
  610. /*!
  611. \brief configure the system clock to 108M by PLL which selects HXTAL(8M) as its clock source
  612. \param[in] none
  613. \param[out] none
  614. \retval none
  615. */
  616. static void system_clock_108m_hxtal(void)
  617. {
  618. uint32_t timeout = 0U;
  619. uint32_t stab_flag = 0U;
  620. /* enable HXTAL */
  621. RCU_CTL |= RCU_CTL_HXTALEN;
  622. /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
  623. do{
  624. timeout++;
  625. stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
  626. }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
  627. /* if fail */
  628. if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
  629. while(1){
  630. }
  631. }
  632. RCU_APB1EN |= RCU_APB1EN_PMUEN;
  633. PMU_CTL |= PMU_CTL_LDOVS;
  634. /* HXTAL is stable */
  635. /* AHB = SYSCLK */
  636. RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
  637. /* APB2 = AHB/1 */
  638. RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
  639. /* APB1 = AHB/2 */
  640. RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
  641. #if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
  642. /* select HXTAL/2 as clock source */
  643. RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0);
  644. RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0);
  645. /* CK_PLL = (CK_HXTAL/2) * 27 = 108 MHz */
  646. RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
  647. RCU_CFG0 |= RCU_PLL_MUL27;
  648. #elif defined(GD32F30X_CL)
  649. /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */
  650. RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
  651. RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL27);
  652. /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
  653. RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
  654. RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
  655. /* enable PLL1 */
  656. RCU_CTL |= RCU_CTL_PLL1EN;
  657. /* wait till PLL1 is ready */
  658. while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
  659. }
  660. #endif /* GD32F30X_HD and GD32F30X_XD */
  661. /* enable PLL */
  662. RCU_CTL |= RCU_CTL_PLLEN;
  663. /* wait until PLL is stable */
  664. while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
  665. }
  666. /* enable the high-drive to extend the clock frequency to 120 MHz */
  667. PMU_CTL |= PMU_CTL_HDEN;
  668. while(0U == (PMU_CS & PMU_CS_HDRF)){
  669. }
  670. /* select the high-drive mode */
  671. PMU_CTL |= PMU_CTL_HDS;
  672. while(0U == (PMU_CS & PMU_CS_HDSRF)){
  673. }
  674. /* select PLL as system clock */
  675. RCU_CFG0 &= ~RCU_CFG0_SCS;
  676. RCU_CFG0 |= RCU_CKSYSSRC_PLL;
  677. /* wait until PLL is selected as system clock */
  678. while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
  679. }
  680. }
  681. #elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL)
  682. /*!
  683. \brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source
  684. \param[in] none
  685. \param[out] none
  686. \retval none
  687. */
  688. static void system_clock_120m_hxtal(void)
  689. {
  690. uint32_t timeout = 0U;
  691. uint32_t stab_flag = 0U;
  692. /* enable HXTAL */
  693. RCU_CTL |= RCU_CTL_HXTALEN;
  694. /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
  695. do{
  696. timeout++;
  697. stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
  698. }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
  699. /* if fail */
  700. if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
  701. while(1){
  702. }
  703. }
  704. RCU_APB1EN |= RCU_APB1EN_PMUEN;
  705. PMU_CTL |= PMU_CTL_LDOVS;
  706. /* HXTAL is stable */
  707. /* AHB = SYSCLK */
  708. RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
  709. /* APB2 = AHB/1 */
  710. RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
  711. /* APB1 = AHB/2 */
  712. RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
  713. #if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
  714. /* select HXTAL/2 as clock source */
  715. RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0);
  716. RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0);
  717. /* CK_PLL = (CK_HXTAL/2) * 30 = 120 MHz */
  718. RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
  719. RCU_CFG0 |= RCU_PLL_MUL30;
  720. #elif defined(GD32F30X_CL)
  721. /* CK_PLL = (CK_PREDIV0) * 30 = 120 MHz */
  722. RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
  723. RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL30);
  724. /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
  725. RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
  726. RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
  727. /* enable PLL1 */
  728. RCU_CTL |= RCU_CTL_PLL1EN;
  729. /* wait till PLL1 is ready */
  730. while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){
  731. }
  732. #endif /* GD32F30X_HD and GD32F30X_XD */
  733. /* enable PLL */
  734. RCU_CTL |= RCU_CTL_PLLEN;
  735. /* wait until PLL is stable */
  736. while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
  737. }
  738. /* enable the high-drive to extend the clock frequency to 120 MHz */
  739. PMU_CTL |= PMU_CTL_HDEN;
  740. while(0U == (PMU_CS & PMU_CS_HDRF)){
  741. }
  742. /* select the high-drive mode */
  743. PMU_CTL |= PMU_CTL_HDS;
  744. while(0U == (PMU_CS & PMU_CS_HDSRF)){
  745. }
  746. /* select PLL as system clock */
  747. RCU_CFG0 &= ~RCU_CFG0_SCS;
  748. RCU_CFG0 |= RCU_CKSYSSRC_PLL;
  749. /* wait until PLL is selected as system clock */
  750. while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
  751. }
  752. }
  753. #endif /* __SYSTEM_CLOCK_IRC8M */
  754. /*!
  755. \brief update the SystemCoreClock with current core clock retrieved from cpu registers
  756. \param[in] none
  757. \param[out] none
  758. \retval none
  759. */
  760. void SystemCoreClockUpdate (void)
  761. {
  762. uint32_t sws;
  763. uint32_t pllsel, pllpresel, predv0sel, pllmf, ck_src, idx, clk_exp;
  764. /* exponent of AHB, APB1 and APB2 clock divider */
  765. const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
  766. #ifdef GD32F30X_CL
  767. uint32_t predv0, predv1, pll1mf;
  768. #endif /* GD32F30X_CL */
  769. sws = GET_BITS(RCU_CFG0, 2, 3);
  770. switch(sws){
  771. /* IRC8M is selected as CK_SYS */
  772. case SEL_IRC8M:
  773. SystemCoreClock = IRC8M_VALUE;
  774. break;
  775. /* HXTAL is selected as CK_SYS */
  776. case SEL_HXTAL:
  777. SystemCoreClock = HXTAL_VALUE;
  778. break;
  779. /* PLL is selected as CK_SYS */
  780. case SEL_PLL:
  781. /* PLL clock source selection, HXTAL, IRC48M or IRC8M/2 */
  782. pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL);
  783. if (RCU_PLLSRC_HXTAL_IRC48M == pllsel) {
  784. /* PLL clock source is HXTAL or IRC48M */
  785. pllpresel = (RCU_CFG1 & RCU_CFG1_PLLPRESEL);
  786. if(RCU_PLLPRESRC_HXTAL == pllpresel){
  787. /* PLL clock source is HXTAL */
  788. ck_src = HXTAL_VALUE;
  789. }else{
  790. /* PLL clock source is IRC48 */
  791. ck_src = IRC48M_VALUE;
  792. }
  793. #if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
  794. predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0);
  795. /* PREDV0 input source clock divided by 2 */
  796. if(RCU_CFG0_PREDV0 == predv0sel){
  797. ck_src /= 2U;
  798. }
  799. #elif defined(GD32F30X_CL)
  800. predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL);
  801. /* source clock use PLL1 */
  802. if(RCU_PREDV0SRC_CKPLL1 == predv0sel){
  803. predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U;
  804. pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U;
  805. if(17U == pll1mf){
  806. pll1mf = 20U;
  807. }
  808. ck_src = (ck_src / predv1) * pll1mf;
  809. }
  810. predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U;
  811. ck_src /= predv0;
  812. #endif /* GD32F30X_HD and GD32F30X_XD */
  813. }else{
  814. /* PLL clock source is IRC8M/2 */
  815. ck_src = IRC8M_VALUE / 2U;
  816. }
  817. /* PLL multiplication factor */
  818. pllmf = GET_BITS(RCU_CFG0, 18, 21);
  819. if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){
  820. pllmf |= 0x10U;
  821. }
  822. if((RCU_CFG0 & RCU_CFG0_PLLMF_5)){
  823. pllmf |= 0x20U;
  824. }
  825. if( pllmf >= 15U){
  826. pllmf += 1U;
  827. }else{
  828. pllmf += 2U;
  829. }
  830. if(pllmf > 61U){
  831. pllmf = 63U;
  832. }
  833. SystemCoreClock = ck_src * pllmf;
  834. #ifdef GD32F30X_CL
  835. if(15U == pllmf){
  836. SystemCoreClock = (ck_src * 6U) + (ck_src / 2U);
  837. }
  838. #endif /* GD32F30X_CL */
  839. break;
  840. /* IRC8M is selected as CK_SYS */
  841. default:
  842. SystemCoreClock = IRC8M_VALUE;
  843. break;
  844. }
  845. /* calculate AHB clock frequency */
  846. idx = GET_BITS(RCU_CFG0, 4, 7);
  847. clk_exp = ahb_exp[idx];
  848. SystemCoreClock = SystemCoreClock >> clk_exp;
  849. }