main.c 7.5 KB

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  1. /*!
  2. \file main.c
  3. \brief TIMER0 dma burst demo for gd32f30x
  4. \version 2017-02-10, V1.0.0, firmware for GD32F30x
  5. \version 2018-10-10, V1.1.0, firmware for GD32F30x
  6. \version 2018-12-25, V2.0.0, firmware for GD32F30x
  7. \version 2020-09-30, V2.1.0, firmware for GD32F30x
  8. */
  9. /*
  10. Copyright (c) 2020, GigaDevice Semiconductor Inc.
  11. Redistribution and use in source and binary forms, with or without modification,
  12. are permitted provided that the following conditions are met:
  13. 1. Redistributions of source code must retain the above copyright notice, this
  14. list of conditions and the following disclaimer.
  15. 2. Redistributions in binary form must reproduce the above copyright notice,
  16. this list of conditions and the following disclaimer in the documentation
  17. and/or other materials provided with the distribution.
  18. 3. Neither the name of the copyright holder nor the names of its contributors
  19. may be used to endorse or promote products derived from this software without
  20. specific prior written permission.
  21. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22. AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  23. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  24. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  25. INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26. NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  27. PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  28. WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29. ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  30. OF SUCH DAMAGE.
  31. */
  32. #include "gd32f30x.h"
  33. #include <stdio.h>
  34. #include "gd32f307c_eval.h"
  35. #define TIMER0_DMATB ((uint32_t)0x40012C4C)
  36. uint16_t buffer[8] = {99,199,299,399,499,599,699,799};
  37. void gpio_config(void);
  38. void timer_config(void);
  39. void dma_config(void);
  40. /*!
  41. \brief configure the GPIO ports
  42. \param[in] none
  43. \param[out] none
  44. \retval none
  45. */
  46. void gpio_config(void)
  47. {
  48. rcu_periph_clock_enable(RCU_GPIOA);
  49. rcu_periph_clock_enable(RCU_AF);
  50. /*configure PA8(TIMER0 CH0) as alternate function*/
  51. gpio_init(GPIOA,GPIO_MODE_AF_PP,GPIO_OSPEED_50MHZ,GPIO_PIN_8);
  52. /*configure PA9(TIMER0 CH1) as alternate function*/
  53. gpio_init(GPIOA,GPIO_MODE_AF_PP,GPIO_OSPEED_50MHZ,GPIO_PIN_9);
  54. /*configure PA10(TIMER0 CH2) as alternate function*/
  55. gpio_init(GPIOA,GPIO_MODE_AF_PP,GPIO_OSPEED_50MHZ,GPIO_PIN_10);
  56. /*configure PA11(TIMER0 CH3) as alternate function*/
  57. gpio_init(GPIOA,GPIO_MODE_AF_PP,GPIO_OSPEED_50MHZ,GPIO_PIN_11);
  58. }
  59. /*!
  60. \brief configure the DMA peripheral
  61. \param[in] none
  62. \param[out] none
  63. \retval none
  64. */
  65. void dma_config(void)
  66. {
  67. dma_parameter_struct dma_init_struct;
  68. /* enable DMA clock */
  69. rcu_periph_clock_enable(RCU_DMA0);
  70. /* initialize DMA channel4 */
  71. dma_deinit(DMA0,DMA_CH4);
  72. /* DMA channel4 initialize */
  73. dma_init_struct.periph_addr = (uint32_t)TIMER0_DMATB;
  74. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
  75. dma_init_struct.memory_addr = (uint32_t)buffer;
  76. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
  77. dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_16BIT;
  78. dma_init_struct.memory_width = DMA_MEMORY_WIDTH_16BIT;
  79. dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
  80. dma_init_struct.number = 8;
  81. dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
  82. dma_init(DMA0,DMA_CH4,&dma_init_struct);
  83. dma_circulation_enable(DMA0,DMA_CH4);
  84. /* enable DMA channel4 */
  85. dma_channel_enable(DMA0,DMA_CH4);
  86. }
  87. /*!
  88. \brief configure the TIMER peripheral
  89. \param[in] none
  90. \param[out] none
  91. \retval none
  92. */
  93. void timer_config(void)
  94. {
  95. /* TIMER0 DMA transfer example -------------------------------------------------
  96. TIMER0CLK = 120MHz, prescaler = 119
  97. TIMER0 counter clock = systemcoreclock/120 = 1MHz.
  98. The objective is to configure TIMER0 channel 0~3(PA8~PA11) to generate PWM signal.
  99. capture compare register 0~3 are to be updated twice per circle.On the first update
  100. DMA request, data1 is transferred to CH0CV, data2 is transferred to CH1CV, data3 is
  101. transferred to CH2CV,data4 is transferred to CH3CV and duty cycle(10%,20%,30%,40%).
  102. On the second update DMA request, data5 is transferred to CH0CV, data6 is transferred
  103. to CH1CV, data7 is transferred to CH2CV,data8 is transferred to CH3CV and duty cycle
  104. (50%,60%,70%,80%).
  105. -----------------------------------------------------------------------------*/
  106. timer_oc_parameter_struct timer_ocintpara;
  107. timer_parameter_struct timer_initpara;
  108. rcu_periph_clock_enable(RCU_TIMER0);
  109. timer_deinit(TIMER0);
  110. /* TIMER0 configuration */
  111. timer_initpara.prescaler = 119;
  112. timer_initpara.alignedmode = TIMER_COUNTER_EDGE;
  113. timer_initpara.counterdirection = TIMER_COUNTER_UP;
  114. timer_initpara.period = 999;
  115. timer_initpara.clockdivision = TIMER_CKDIV_DIV1;
  116. timer_initpara.repetitioncounter = 0;
  117. timer_init(TIMER0,&timer_initpara);
  118. timer_ocintpara.outputstate = TIMER_CCX_ENABLE;
  119. timer_ocintpara.outputnstate = TIMER_CCXN_DISABLE;
  120. timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH;
  121. timer_ocintpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH;
  122. timer_ocintpara.ocidlestate = TIMER_OC_IDLE_STATE_HIGH;
  123. timer_ocintpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW;
  124. timer_channel_output_config(TIMER0,TIMER_CH_0,&timer_ocintpara);
  125. timer_channel_output_config(TIMER0,TIMER_CH_1,&timer_ocintpara);
  126. timer_channel_output_config(TIMER0,TIMER_CH_2,&timer_ocintpara);
  127. timer_channel_output_config(TIMER0,TIMER_CH_3,&timer_ocintpara);
  128. /* CH0 configuration in PWM0 mode */
  129. timer_channel_output_pulse_value_config(TIMER0,TIMER_CH_0,buffer[0]);
  130. timer_channel_output_mode_config(TIMER0,TIMER_CH_0,TIMER_OC_MODE_PWM0);
  131. timer_channel_output_shadow_config(TIMER0,TIMER_CH_0,TIMER_OC_SHADOW_DISABLE);
  132. /* CH1 configuration in PWM0 mode */
  133. timer_channel_output_pulse_value_config(TIMER0,TIMER_CH_1,buffer[0]);
  134. timer_channel_output_mode_config(TIMER0,TIMER_CH_1,TIMER_OC_MODE_PWM0);
  135. timer_channel_output_shadow_config(TIMER0,TIMER_CH_1,TIMER_OC_SHADOW_DISABLE);
  136. /* CH2 configuration in PWM0 mode */
  137. timer_channel_output_pulse_value_config(TIMER0,TIMER_CH_2,buffer[0]);
  138. timer_channel_output_mode_config(TIMER0,TIMER_CH_2,TIMER_OC_MODE_PWM0);
  139. timer_channel_output_shadow_config(TIMER0,TIMER_CH_2,TIMER_OC_SHADOW_DISABLE);
  140. /* CH3 configuration in PWM0 mode */
  141. timer_channel_output_pulse_value_config(TIMER0,TIMER_CH_3,buffer[0]);
  142. timer_channel_output_mode_config(TIMER0,TIMER_CH_3,TIMER_OC_MODE_PWM0);
  143. timer_channel_output_shadow_config(TIMER0,TIMER_CH_3,TIMER_OC_SHADOW_DISABLE);
  144. /* TIMER0 primary output enable */
  145. timer_primary_output_config(TIMER0,ENABLE);
  146. /* TIMER0 update DMA request enable */
  147. timer_dma_transfer_config(TIMER0,TIMER_DMACFG_DMATA_CH0CV,TIMER_DMACFG_DMATC_4TRANSFER);
  148. timer_dma_enable(TIMER0,TIMER_DMA_UPD);
  149. /* auto-reload preload enable */
  150. timer_auto_reload_shadow_enable(TIMER0);
  151. /* TIMER0 counter enable */
  152. timer_enable(TIMER0);
  153. }
  154. /*!
  155. \brief main function
  156. \param[in] none
  157. \param[out] none
  158. \retval none
  159. */
  160. int main(void)
  161. {
  162. gpio_config();
  163. dma_config();
  164. timer_config();
  165. while (1);
  166. }