i2c.c 9.5 KB

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  1. /*!
  2. \file i2c.c
  3. \brief I2C configuration file
  4. \version 2022-05-30, V1.0.0, firmware for GD32F30x
  5. */
  6. /*
  7. Copyright (c) 2022, GigaDevice Semiconductor Inc.
  8. Redistribution and use in source and binary forms, with or without modification,
  9. are permitted provided that the following conditions are met:
  10. 1. Redistributions of source code must retain the above copyright notice, this
  11. list of conditions and the following disclaimer.
  12. 2. Redistributions in binary form must reproduce the above copyright notice,
  13. this list of conditions and the following disclaimer in the documentation
  14. and/or other materials provided with the distribution.
  15. 3. Neither the name of the copyright holder nor the names of its contributors
  16. may be used to endorse or promote products derived from this software without
  17. specific prior written permission.
  18. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  19. AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  20. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  22. INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23. NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  24. PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  25. WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  26. ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  27. OF SUCH DAMAGE.
  28. */
  29. #include "gd32f30x.h"
  30. #include "i2c.h"
  31. #include <stdio.h>
  32. #include "systick.h"
  33. uint8_t i2c_read_process = 0;
  34. uint8_t i2c_write_process = 0;
  35. /*!
  36. \brief configure the GPIO ports
  37. \param[in] none
  38. \param[out] none
  39. \retval none
  40. */
  41. void gpio_config(void)
  42. {
  43. /* enable GPIOB clock */
  44. rcu_periph_clock_enable(RCU_GPIO_I2C);
  45. /* connect I2C_SCL_PIN to I2C_SCL */
  46. /* connect I2C_SDA_PIN to I2C_SDA */
  47. gpio_init(I2C_SCL_PORT, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, I2C_SCL_PIN);
  48. gpio_init(I2C_SDA_PORT, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, I2C_SDA_PIN);
  49. }
  50. /*!
  51. \brief configure the I2CX interfaces
  52. \param[in] none
  53. \param[out] none
  54. \retval none
  55. */
  56. void i2c_config(void)
  57. {
  58. /* enable I2C clock */
  59. rcu_periph_clock_enable(RCU_I2C);
  60. /* configure I2C clock */
  61. i2c_clock_config(I2CX, I2C_SPEED, I2C_DTCY_2);
  62. /* configure I2C address */
  63. i2c_mode_addr_config(I2CX, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, I2CX_SLAVE_ADDRESS7);
  64. /* enable I2CX */
  65. i2c_enable(I2CX);
  66. /* enable acknowledge */
  67. i2c_ack_config(I2CX, I2C_ACK_ENABLE);
  68. }
  69. /*!
  70. \brief handle I2CX event interrupt request
  71. \param[in] none
  72. \param[out] none
  73. \retval none
  74. */
  75. void i2cx_event_irq_handler(void)
  76. {
  77. if(RESET == i2c_process_flag) {
  78. switch(i2c_write_process) {
  79. case I2C_SEND_ADDRESS_FIRST:
  80. if(i2c_interrupt_flag_get(I2CX, I2C_INT_FLAG_SBSEND)) {
  81. /* send slave address */
  82. i2c_master_addressing(I2CX, I2CX_SLAVE_ADDRESS7, I2C_TRANSMITTER);
  83. i2c_write_process = I2C_CLEAR_ADDRESS_FLAG_FIRST;
  84. }
  85. break;
  86. case I2C_CLEAR_ADDRESS_FLAG_FIRST:
  87. if(i2c_interrupt_flag_get(I2CX, I2C_INT_FLAG_ADDSEND)) {
  88. /*clear ADDSEND bit */
  89. i2c_interrupt_flag_clear(I2CX, I2C_INT_FLAG_ADDSEND);
  90. i2c_write_process = I2C_TRANSMIT_WRITE_READ_ADD;
  91. }
  92. break;
  93. case I2C_TRANSMIT_WRITE_READ_ADD:
  94. if(i2c_interrupt_flag_get(I2CX, I2C_INT_FLAG_TBE)) {
  95. i2c_data_transmit(I2CX, i2c_write_dress);
  96. /* wait until BTC bit is set */
  97. while(!i2c_flag_get(I2CX, I2C_FLAG_BTC));
  98. i2c_write_process = I2C_TRANSMIT_DATA;
  99. }
  100. break;
  101. case I2C_TRANSMIT_DATA:
  102. if(i2c_interrupt_flag_get(I2CX, I2C_INT_FLAG_TBE)) {
  103. /* the master sends a data byte */
  104. i2c_data_transmit(I2CX, *i2c_write++);
  105. i2c_nbytes--;
  106. if(RESET == i2c_nbytes) {
  107. i2c_write_process = I2C_STOP;
  108. }
  109. }
  110. break;
  111. case I2C_STOP:
  112. /* the master sends a stop condition to I2C bus */
  113. i2c_stop_on_bus(I2CX);
  114. /* disable the I2CX interrupt */
  115. i2c_interrupt_disable(I2CX, I2C_INT_ERR);
  116. i2c_interrupt_disable(I2CX, I2C_INT_BUF);
  117. i2c_interrupt_disable(I2CX, I2C_INT_EV);
  118. i2c_write_process = I2C_SEND_ADDRESS_FIRST;
  119. break;
  120. default:
  121. break;
  122. }
  123. } else if(SET == i2c_process_flag) {
  124. switch(i2c_read_process) {
  125. case I2C_SEND_ADDRESS_FIRST:
  126. if(i2c_interrupt_flag_get(I2CX, I2C_INT_FLAG_SBSEND)) {
  127. /* send slave address */
  128. i2c_master_addressing(I2CX, I2CX_SLAVE_ADDRESS7, I2C_TRANSMITTER);
  129. i2c_read_process = I2C_CLEAR_ADDRESS_FLAG_FIRST;
  130. }
  131. break;
  132. case I2C_CLEAR_ADDRESS_FLAG_FIRST:
  133. if(i2c_interrupt_flag_get(I2CX, I2C_INT_FLAG_ADDSEND)) {
  134. /*clear ADDSEND bit */
  135. i2c_interrupt_flag_clear(I2CX, I2C_INT_FLAG_ADDSEND);
  136. i2c_read_process = I2C_TRANSMIT_WRITE_READ_ADD;
  137. }
  138. break;
  139. case I2C_TRANSMIT_WRITE_READ_ADD:
  140. if(i2c_interrupt_flag_get(I2CX, I2C_INT_FLAG_TBE)) {
  141. i2c_data_transmit(I2CX, i2c_read_dress);
  142. /* wait until BTC bit is set */
  143. while(!i2c_flag_get(I2CX, I2C_FLAG_BTC));
  144. /* send a start condition to I2C bus */
  145. i2c_start_on_bus(I2CX);
  146. i2c_read_process = I2C_SEND_ADDRESS_SECOND;
  147. }
  148. break;
  149. case I2C_SEND_ADDRESS_SECOND:
  150. if(i2c_interrupt_flag_get(I2CX, I2C_INT_FLAG_SBSEND)) {
  151. i2c_master_addressing(I2CX, I2CX_SLAVE_ADDRESS7, I2C_RECEIVER);
  152. if(i2c_nbytes < 3) {
  153. /* disable acknowledge */
  154. i2c_ack_config(I2CX, I2C_ACK_DISABLE);
  155. }
  156. i2c_read_process = I2C_CLEAR_ADDRESS_FLAG_SECOND;
  157. }
  158. break;
  159. case I2C_CLEAR_ADDRESS_FLAG_SECOND:
  160. if(i2c_interrupt_flag_get(I2CX, I2C_INT_FLAG_ADDSEND)) {
  161. /*clear ADDSEND bit */
  162. i2c_interrupt_flag_clear(I2CX, I2C_INT_FLAG_ADDSEND);
  163. if((1 == i2c_nbytes) || (2 == i2c_nbytes)) {
  164. /* clear the ACKEN before the ADDSEND is cleared */
  165. i2c_ack_config(I2CX, I2C_ACK_DISABLE);
  166. }
  167. i2c_read_process = I2C_TRANSMIT_DATA;
  168. }
  169. break;
  170. case I2C_TRANSMIT_DATA:
  171. if(i2c_interrupt_flag_get(I2CX, I2C_INT_FLAG_RBNE)) {
  172. if(i2c_nbytes > 0) {
  173. if(i2c_nbytes == 3) {
  174. /* wait until BTC bit is set */
  175. while(!i2c_flag_get(I2CX, I2C_FLAG_BTC));
  176. /* disable acknowledge */
  177. i2c_ack_config(I2CX, I2C_ACK_DISABLE);
  178. }
  179. /* read a byte from the EEPROM */
  180. *i2c_read = i2c_data_receive(I2CX);
  181. i2c_read++;
  182. i2c_nbytes--;
  183. if(i2c_nbytes == 0) {
  184. i2c_read_process = I2C_SEND_ADDRESS_FIRST;
  185. /* the master sends a stop condition to I2C bus */
  186. i2c_stop_on_bus(I2CX);
  187. /* disable the I2CX interrupt */
  188. i2c_interrupt_disable(I2CX, I2C_INT_ERR);
  189. i2c_interrupt_disable(I2CX, I2C_INT_BUF);
  190. i2c_interrupt_disable(I2CX, I2C_INT_EV);
  191. i2c_process_flag = RESET;
  192. }
  193. }
  194. }
  195. break;
  196. default:
  197. break;
  198. }
  199. }
  200. }
  201. /*!
  202. \brief handle I2CX error interrupt request
  203. \param[in] none
  204. \param[out] none
  205. \retval none
  206. */
  207. void i2cx_error_irq_handler(void)
  208. {
  209. /* no acknowledge received */
  210. if(i2c_interrupt_flag_get(I2CX, I2C_INT_FLAG_AERR)) {
  211. i2c_interrupt_flag_clear(I2CX, I2C_INT_FLAG_AERR);
  212. }
  213. /* SMBus alert */
  214. if(i2c_interrupt_flag_get(I2CX, I2C_INT_FLAG_SMBALT)) {
  215. i2c_interrupt_flag_clear(I2CX, I2C_INT_FLAG_SMBALT);
  216. }
  217. /* bus timeout in SMBus mode */
  218. if(i2c_interrupt_flag_get(I2CX, I2C_INT_FLAG_SMBTO)) {
  219. i2c_interrupt_flag_clear(I2CX, I2C_INT_FLAG_SMBTO);
  220. }
  221. /* over-run or under-run when SCL stretch is disabled */
  222. if(i2c_interrupt_flag_get(I2CX, I2C_INT_FLAG_OUERR)) {
  223. i2c_interrupt_flag_clear(I2CX, I2C_INT_FLAG_OUERR);
  224. }
  225. /* arbitration lost */
  226. if(i2c_interrupt_flag_get(I2CX, I2C_INT_FLAG_LOSTARB)) {
  227. i2c_interrupt_flag_clear(I2CX, I2C_INT_FLAG_LOSTARB);
  228. }
  229. /* bus error */
  230. if(i2c_interrupt_flag_get(I2CX, I2C_INT_FLAG_BERR)) {
  231. i2c_interrupt_flag_clear(I2CX, I2C_INT_FLAG_BERR);
  232. }
  233. /* CRC value doesn't match */
  234. if(i2c_interrupt_flag_get(I2CX, I2C_INT_FLAG_PECERR)) {
  235. i2c_interrupt_flag_clear(I2CX, I2C_INT_FLAG_PECERR);
  236. }
  237. /* disable the error interrupt */
  238. i2c_interrupt_disable(I2CX, I2C_INT_ERR);
  239. i2c_interrupt_disable(I2CX, I2C_INT_BUF);
  240. i2c_interrupt_disable(I2CX, I2C_INT_EV);
  241. }