caowencai 46500e86d7 LCD_relay_init 7 месяцев назад
..
gd32f30x_libopt.h 46500e86d7 LCD_relay_init 7 месяцев назад
main.c 46500e86d7 LCD_relay_init 7 месяцев назад
readme.txt 46500e86d7 LCD_relay_init 7 месяцев назад

readme.txt

/*!
\file readme.txt
\brief description of DMA ram to ram

\version 2017-02-10, V1.0.0, firmware for GD32F30x
\version 2018-10-10, V1.1.0, firmware for GD32F30x
\version 2018-12-25, V2.0.0, firmware for GD32F30x
\version 2020-09-30, V2.1.0, firmware for GD32F30x
*/

/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.

Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/

This example is based on the GD32307C-EVAL-V1.1 board, it provides a description
of how to use DMA channel(1 to 4) to transfer data from RAM to RAM.DMA Channel(1 to 4) is
configured to transfer the contents of data buffer stored in "source_address" to the
reception buffer declared in RAM(destination_address1~destination_address4).

The start of transfer is triggered by software. At the end of the transfer, a comparison
between the source and destination buffers is done to check that all data have been correctly
transferred.If transfer correctly the corresponding LED(2~5) light.If transfer do not correcly,
the corresponding LED is off.