wenkong_junshi/Examples/DBG/DBG_timer1_stop

/*!
\file readme.txt
\brief description of the DBG demo

\version 2017-02-10, V1.0.0, firmware for GD32F30x
\version 2018-10-10, V1.1.0, firmware for GD32F30x
\version 2018-12-25, V2.0.0, firmware for GD32F30x
\version 2020-09-30, V2.1.0, firmware for GD32F30x
*/

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*/

This demo is based on the GD32307C-EVAL-V1.1 board. It shows that LED2 will toggle
every second when system start up. when the TIMER1_HOLD bit in DBG control register(DBG_CTL0)
is set and the core halted, the TIMER1 counter stop counting and the PWM outputs of all
channels are stopped as well. It's benefit for debuging.

The TIMER1 counter clock used is 1MHz.
The Three Duty cycles are computed as the following description:
The channel 1 duty cycle is set to 25%
The channel 2 duty cycle is set to 50%
The channel 3 duty cycle is set to 75%

Connect the TIMER1 pins to an oscilloscope and monitor the different waveforms:
- TIMER1_CH1 pin (PB3)
- TIMER1_CH2 pin (PB10)
- TIMER1_CH3 pin (PB11)

For Keil,in debug mode,when the core is stopped,update the register window for TIMER1,
you will see that the count value will not change. And at the same time,the PWM outputs of
all the channels of TIMER1 will be stopped.