drv_usbd_int.c 14 KB

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  1. /*!
  2. \file drv_usbd_int.c
  3. \brief USB device mode interrupt routines
  4. \version 2023-06-30, V2.1.6, firmware for GD32F30x
  5. */
  6. /*
  7. Copyright (c) 2023, GigaDevice Semiconductor Inc.
  8. Redistribution and use in source and binary forms, with or without modification,
  9. are permitted provided that the following conditions are met:
  10. 1. Redistributions of source code must retain the above copyright notice, this
  11. list of conditions and the following disclaimer.
  12. 2. Redistributions in binary form must reproduce the above copyright notice,
  13. this list of conditions and the following disclaimer in the documentation
  14. and/or other materials provided with the distribution.
  15. 3. Neither the name of the copyright holder nor the names of its contributors
  16. may be used to endorse or promote products derived from this software without
  17. specific prior written permission.
  18. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  19. AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  20. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  22. INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23. NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  24. PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  25. WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  26. ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  27. OF SUCH DAMAGE.
  28. */
  29. #include "usbd_conf.h"
  30. #include "drv_usbd_int.h"
  31. #include "usbd_transc.h"
  32. /* local function prototypes ('static') */
  33. static uint32_t usbd_int_epout (usb_core_driver *udev);
  34. static uint32_t usbd_int_epin (usb_core_driver *udev);
  35. static uint32_t usbd_int_rxfifo (usb_core_driver *udev);
  36. static uint32_t usbd_int_reset (usb_core_driver *udev);
  37. static uint32_t usbd_int_enumfinish (usb_core_driver *udev);
  38. static uint32_t usbd_int_suspend (usb_core_driver *udev);
  39. static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num);
  40. static const uint8_t USB_SPEED[4] =
  41. {
  42. [DSTAT_EM_HS_PHY_30MHZ_60MHZ] = (uint8_t)USB_SPEED_HIGH,
  43. [DSTAT_EM_FS_PHY_30MHZ_60MHZ] = (uint8_t)USB_SPEED_FULL,
  44. [DSTAT_EM_FS_PHY_48MHZ] = (uint8_t)USB_SPEED_FULL,
  45. [DSTAT_EM_LS_PHY_6MHZ] = (uint8_t)USB_SPEED_LOW
  46. };
  47. /*!
  48. \brief USB device-mode interrupts global service routine handler
  49. \param[in] udev: pointer to USB device instance
  50. \param[out] none
  51. \retval none
  52. */
  53. void usbd_isr (usb_core_driver *udev)
  54. {
  55. if (HOST_MODE != (udev->regs.gr->GINTF & GINTF_COPM)) {
  56. uint32_t intr = udev->regs.gr->GINTF;
  57. intr &= udev->regs.gr->GINTEN;
  58. /* there are no interrupts, avoid spurious interrupt */
  59. if (!intr) {
  60. return;
  61. }
  62. /* OUT endpoints interrupts */
  63. if (intr & GINTF_OEPIF) {
  64. (void)usbd_int_epout (udev);
  65. }
  66. /* IN endpoints interrupts */
  67. if (intr & GINTF_IEPIF) {
  68. (void)usbd_int_epin (udev);
  69. }
  70. /* suspend interrupt */
  71. if (intr & GINTF_SP) {
  72. (void)usbd_int_suspend (udev);
  73. }
  74. /* wakeup interrupt */
  75. if (intr & GINTF_WKUPIF) {
  76. if(USBD_SUSPENDED == udev->dev.cur_status){
  77. /* inform upper layer by the resume event */
  78. udev->dev.cur_status = udev->dev.backup_status;
  79. }
  80. /* clear interrupt */
  81. udev->regs.gr->GINTF = GINTF_WKUPIF;
  82. }
  83. /* start of frame interrupt */
  84. if (intr & GINTF_SOF) {
  85. if (udev->dev.class_core->SOF) {
  86. (void)udev->dev.class_core->SOF(udev);
  87. }
  88. /* clear interrupt */
  89. udev->regs.gr->GINTF = GINTF_SOF;
  90. }
  91. /* receive FIFO not empty interrupt */
  92. if (intr & GINTF_RXFNEIF) {
  93. (void)usbd_int_rxfifo (udev);
  94. }
  95. /* USB reset interrupt */
  96. if (intr & GINTF_RST) {
  97. (void)usbd_int_reset (udev);
  98. }
  99. /* enumeration has been done interrupt */
  100. if (intr & GINTF_ENUMFIF) {
  101. (void)usbd_int_enumfinish (udev);
  102. }
  103. /* incomplete synchronization IN transfer interrupt*/
  104. if (intr & GINTF_ISOINCIF) {
  105. if (NULL != udev->dev.class_core->incomplete_isoc_in) {
  106. (void)udev->dev.class_core->incomplete_isoc_in(udev);
  107. }
  108. /* Clear interrupt */
  109. udev->regs.gr->GINTF = GINTF_ISOINCIF;
  110. }
  111. /* incomplete synchronization OUT transfer interrupt*/
  112. if (intr & GINTF_ISOONCIF) {
  113. if (NULL != udev->dev.class_core->incomplete_isoc_out) {
  114. (void)udev->dev.class_core->incomplete_isoc_out(udev);
  115. }
  116. /* clear interrupt */
  117. udev->regs.gr->GINTF = GINTF_ISOONCIF;
  118. }
  119. #ifdef VBUS_SENSING_ENABLED
  120. /* Session request interrupt */
  121. if (intr & GINTF_SESIF) {
  122. udev->regs.gr->GINTF = GINTF_SESIF;
  123. }
  124. /* OTG mode interrupt */
  125. if (intr & GINTF_OTGIF) {
  126. if(udev->regs.gr->GOTGINTF & GOTGINTF_SESEND) {
  127. }
  128. /* Clear OTG interrupt */
  129. udev->regs.gr->GINTF = GINTF_OTGIF;
  130. }
  131. #endif /* VBUS_SENSING_ENABLED */
  132. }
  133. }
  134. /*!
  135. \brief indicates that an OUT endpoint has a pending interrupt
  136. \param[in] udev: pointer to USB device instance
  137. \param[out] none
  138. \retval operation status
  139. */
  140. static uint32_t usbd_int_epout (usb_core_driver *udev)
  141. {
  142. uint32_t epintnum = 0U;
  143. uint8_t ep_num = 0U;
  144. for (epintnum = usb_oepintnum_read (udev); epintnum; epintnum >>= 1, ep_num++) {
  145. if (epintnum & 0x01U) {
  146. __IO uint32_t oepintr = usb_oepintr_read (udev, ep_num);
  147. /* transfer complete interrupt */
  148. if (oepintr & DOEPINTF_TF) {
  149. /* clear the bit in DOEPINTF for this interrupt */
  150. udev->regs.er_out[ep_num]->DOEPINTF = DOEPINTF_TF;
  151. /* inform upper layer: data ready */
  152. (void)usbd_out_transc (udev, ep_num);
  153. }
  154. /* setup phase finished interrupt (control endpoints) */
  155. if (oepintr & DOEPINTF_STPF) {
  156. /* inform the upper layer that a setup packet is available */
  157. (void)usbd_setup_transc (udev);
  158. udev->regs.er_out[ep_num]->DOEPINTF = DOEPINTF_STPF;
  159. }
  160. }
  161. }
  162. return 1U;
  163. }
  164. /*!
  165. \brief indicates that an IN endpoint has a pending interrupt
  166. \param[in] udev: pointer to USB device instance
  167. \param[out] none
  168. \retval operation status
  169. */
  170. static uint32_t usbd_int_epin (usb_core_driver *udev)
  171. {
  172. uint32_t epintnum = 0U;
  173. uint8_t ep_num = 0U;
  174. for (epintnum = usb_iepintnum_read (udev); epintnum; epintnum >>= 1, ep_num++) {
  175. if (epintnum & 0x1U) {
  176. __IO uint32_t iepintr = usb_iepintr_read (udev, ep_num);
  177. if (iepintr & DIEPINTF_TF) {
  178. udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TF;
  179. /* data transmission is completed */
  180. (void)usbd_in_transc (udev, ep_num);
  181. }
  182. if (iepintr & DIEPINTF_TXFE) {
  183. usbd_emptytxfifo_write (udev, (uint32_t)ep_num);
  184. udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TXFE;
  185. }
  186. }
  187. }
  188. return 1U;
  189. }
  190. /*!
  191. \brief handle the RX status queue level interrupt
  192. \param[in] udev: pointer to USB device instance
  193. \param[out] none
  194. \retval operation status
  195. */
  196. static uint32_t usbd_int_rxfifo (usb_core_driver *udev)
  197. {
  198. usb_transc *transc = NULL;
  199. uint8_t data_PID = 0U;
  200. uint32_t bcount = 0U;
  201. __IO uint32_t devrxstat = 0U;
  202. /* disable the Rx status queue non-empty interrupt */
  203. udev->regs.gr->GINTEN &= ~GINTEN_RXFNEIE;
  204. /* get the status from the top of the FIFO */
  205. devrxstat = udev->regs.gr->GRSTATP;
  206. uint8_t ep_num = (uint8_t)(devrxstat & GRSTATRP_EPNUM);
  207. transc = &udev->dev.transc_out[ep_num];
  208. bcount = (devrxstat & GRSTATRP_BCOUNT) >> 4U;
  209. data_PID = (uint8_t)((devrxstat & GRSTATRP_DPID) >> 15U);
  210. switch ((devrxstat & GRSTATRP_RPCKST) >> 17U) {
  211. case RSTAT_GOUT_NAK:
  212. break;
  213. case RSTAT_DATA_UPDT:
  214. if (bcount > 0U) {
  215. (void)usb_rxfifo_read (&udev->regs, transc->xfer_buf, (uint16_t)bcount);
  216. transc->xfer_buf += bcount;
  217. transc->xfer_count += bcount;
  218. }
  219. break;
  220. case RSTAT_XFER_COMP:
  221. /* trigger the OUT endpoint interrupt */
  222. break;
  223. case RSTAT_SETUP_COMP:
  224. /* trigger the OUT endpoint interrupt */
  225. break;
  226. case RSTAT_SETUP_UPDT:
  227. if ((0U == transc->ep_addr.num) && (8U == bcount) && (DPID_DATA0 == data_PID)) {
  228. /* copy the setup packet received in FIFO into the setup buffer in RAM */
  229. (void)usb_rxfifo_read (&udev->regs, (uint8_t *)&udev->dev.control.req, (uint16_t)bcount);
  230. transc->xfer_count += bcount;
  231. }
  232. break;
  233. default:
  234. break;
  235. }
  236. /* enable the Rx status queue level interrupt */
  237. udev->regs.gr->GINTEN |= GINTEN_RXFNEIE;
  238. return 1U;
  239. }
  240. /*!
  241. \brief handle USB reset interrupt
  242. \param[in] udev: pointer to USB device instance
  243. \param[out] none
  244. \retval status
  245. */
  246. static uint32_t usbd_int_reset (usb_core_driver *udev)
  247. {
  248. uint32_t i;
  249. /* clear the remote wakeup signaling */
  250. udev->regs.dr->DCTL &= ~DCTL_RWKUP;
  251. /* flush the Tx FIFO */
  252. (void)usb_txfifo_flush (&udev->regs, 0U);
  253. for (i = 0U; i < udev->bp.num_ep; i++) {
  254. udev->regs.er_in[i]->DIEPINTF = 0xFFU;
  255. udev->regs.er_out[i]->DOEPINTF = 0xFFU;
  256. }
  257. /* clear all pending device endpoint interrupts */
  258. udev->regs.dr->DAEPINT = 0xFFFFFFFFU;
  259. /* enable endpoint 0 interrupts */
  260. udev->regs.dr->DAEPINTEN = 1U | (1U << 16U);
  261. /* enable OUT endpoint interrupts */
  262. udev->regs.dr->DOEPINTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN;
  263. /* enable IN endpoint interrupts */
  264. udev->regs.dr->DIEPINTEN = DIEPINTEN_TFEN;
  265. /* reset device address */
  266. udev->regs.dr->DCFG &= ~DCFG_DAR;
  267. /* configure endpoint 0 to receive SETUP packets */
  268. usb_ctlep_startout (udev);
  269. /* clear USB reset interrupt */
  270. udev->regs.gr->GINTF = GINTF_RST;
  271. udev->dev.transc_out[0] = (usb_transc) {
  272. .ep_type = USB_EPTYPE_CTRL,
  273. .max_len = USB_FS_EP0_MAX_LEN
  274. };
  275. (void)usb_transc_active (udev, &udev->dev.transc_out[0]);
  276. udev->dev.transc_in[0] = (usb_transc) {
  277. .ep_addr = {
  278. .dir = 1U
  279. },
  280. .ep_type = USB_EPTYPE_CTRL,
  281. .max_len = USB_FS_EP0_MAX_LEN
  282. };
  283. (void)usb_transc_active (udev, &udev->dev.transc_in[0]);
  284. /* upon reset call user call back */
  285. udev->dev.cur_status = (uint8_t)USBD_DEFAULT;
  286. return 1U;
  287. }
  288. /*!
  289. \brief handle USB speed enumeration finish interrupt
  290. \param[in] udev: pointer to USB device instance
  291. \param[out] none
  292. \retval status
  293. */
  294. static uint32_t usbd_int_enumfinish (usb_core_driver *udev)
  295. {
  296. uint8_t enum_speed = (uint8_t)((udev->regs.dr->DSTAT & DSTAT_ES) >> 1U);
  297. udev->regs.dr->DCTL &= ~DCTL_CGINAK;
  298. udev->regs.dr->DCTL |= DCTL_CGINAK;
  299. udev->regs.gr->GUSBCS &= ~GUSBCS_UTT;
  300. /* set USB turn-around time based on device speed and PHY interface */
  301. if (USB_SPEED[enum_speed] == (uint8_t)USB_SPEED_HIGH) {
  302. udev->bp.core_speed = (uint8_t)USB_SPEED_HIGH;
  303. udev->regs.gr->GUSBCS |= 0x09U << 10U;
  304. } else {
  305. udev->bp.core_speed = (uint8_t)USB_SPEED_FULL;
  306. udev->regs.gr->GUSBCS |= 0x05U << 10U;
  307. }
  308. /* clear interrupt */
  309. udev->regs.gr->GINTF = GINTF_ENUMFIF;
  310. return 1U;
  311. }
  312. /*!
  313. \brief USB suspend interrupt handler
  314. \param[in] udev: pointer to USB device instance
  315. \param[out] none
  316. \retval operation status
  317. */
  318. static uint32_t usbd_int_suspend (usb_core_driver *udev)
  319. {
  320. __IO uint8_t low_power = udev->bp.low_power;
  321. __IO uint8_t suspend = (uint8_t)(udev->regs.dr->DSTAT & DSTAT_SPST);
  322. __IO uint8_t is_configured = (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED)? 1U : 0U;
  323. udev->dev.backup_status = udev->dev.cur_status;
  324. udev->dev.cur_status = (uint8_t)USBD_SUSPENDED;
  325. if (low_power && suspend && is_configured) {
  326. /* switch-off the OTG clocks */
  327. *udev->regs.PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK;
  328. /* enter DEEP_SLEEP mode with LDO in low power mode */
  329. pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, PMU_LOWDRIVER_DISABLE, WFI_CMD);
  330. }
  331. /* clear interrupt */
  332. udev->regs.gr->GINTF = GINTF_SP;
  333. return 1U;
  334. }
  335. /*!
  336. \brief check FIFO for the next packet to be loaded
  337. \param[in] udev: pointer to USB device instance
  338. \param[in] ep_num: endpoint identifier which is in (0..3)
  339. \param[out] none
  340. \retval status
  341. */
  342. static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num)
  343. {
  344. uint32_t len;
  345. uint32_t word_count;
  346. usb_transc *transc = &udev->dev.transc_in[ep_num];
  347. len = transc->xfer_len - transc->xfer_count;
  348. /* get the data length to write */
  349. if (len > transc->max_len) {
  350. len = transc->max_len;
  351. }
  352. word_count = (len + 3U) / 4U;
  353. while (((udev->regs.er_in[ep_num]->DIEPTFSTAT & DIEPTFSTAT_IEPTFS) >= word_count) && \
  354. (transc->xfer_count < transc->xfer_len)) {
  355. len = transc->xfer_len - transc->xfer_count;
  356. if (len > transc->max_len) {
  357. len = transc->max_len;
  358. }
  359. /* write FIFO in word(4bytes) */
  360. word_count = (len + 3U) / 4U;
  361. /* write the FIFO */
  362. (void)usb_txfifo_write (&udev->regs, transc->xfer_buf, (uint8_t)ep_num, (uint16_t)len);
  363. transc->xfer_buf += len;
  364. transc->xfer_count += len;
  365. if (transc->xfer_count == transc->xfer_len) {
  366. /* disable the device endpoint FIFO empty interrupt */
  367. udev->regs.dr->DIEPFEINTEN &= ~(0x01U << ep_num);
  368. }
  369. }
  370. return 1U;
  371. }