drv_usb_dev.c 17 KB

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  1. /*!
  2. \file drv_usb_dev.c
  3. \brief USB device mode low level driver
  4. \version 2023-06-30, V2.1.6, firmware for GD32F30x
  5. */
  6. /*
  7. Copyright (c) 2023, GigaDevice Semiconductor Inc.
  8. Redistribution and use in source and binary forms, with or without modification,
  9. are permitted provided that the following conditions are met:
  10. 1. Redistributions of source code must retain the above copyright notice, this
  11. list of conditions and the following disclaimer.
  12. 2. Redistributions in binary form must reproduce the above copyright notice,
  13. this list of conditions and the following disclaimer in the documentation
  14. and/or other materials provided with the distribution.
  15. 3. Neither the name of the copyright holder nor the names of its contributors
  16. may be used to endorse or promote products derived from this software without
  17. specific prior written permission.
  18. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  19. AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  20. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  22. INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23. NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  24. PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  25. WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  26. ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  27. OF SUCH DAMAGE.
  28. */
  29. #include "drv_usb_hw.h"
  30. #include "drv_usb_core.h"
  31. #include "drv_usb_dev.h"
  32. /* endpoint 0 max packet length */
  33. static const uint8_t EP0_MAXLEN[4] = {
  34. [DSTAT_EM_HS_PHY_30MHZ_60MHZ] = EP0MPL_64,
  35. [DSTAT_EM_FS_PHY_30MHZ_60MHZ] = EP0MPL_64,
  36. [DSTAT_EM_FS_PHY_48MHZ] = EP0MPL_64,
  37. [DSTAT_EM_LS_PHY_6MHZ] = EP0MPL_8
  38. };
  39. #ifdef USB_FS_CORE
  40. /* USB endpoint Tx FIFO size */
  41. static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] =
  42. {
  43. (uint16_t)TX0_FIFO_FS_SIZE,
  44. (uint16_t)TX1_FIFO_FS_SIZE,
  45. (uint16_t)TX2_FIFO_FS_SIZE,
  46. (uint16_t)TX3_FIFO_FS_SIZE
  47. };
  48. #endif /* USBFS_CORE */
  49. /*!
  50. \brief initialize USB core registers for device mode
  51. \param[in] udev: pointer to USB device
  52. \param[out] none
  53. \retval operation status
  54. */
  55. usb_status usb_devcore_init (usb_core_driver *udev)
  56. {
  57. uint8_t i;
  58. /* restart the PHY clock (maybe don't need to...) */
  59. *udev->regs.PWRCLKCTL = 0U;
  60. /* config periodic frame interval to default value */
  61. udev->regs.dr->DCFG &= ~DCFG_EOPFT;
  62. udev->regs.dr->DCFG |= FRAME_INTERVAL_80;
  63. udev->regs.dr->DCFG &= ~DCFG_DS;
  64. #ifdef USB_FS_CORE
  65. if (udev->bp.core_enum == (uint8_t)USB_CORE_ENUM_FS) {
  66. /* set full-speed PHY */
  67. udev->regs.dr->DCFG |= USB_SPEED_INP_FULL;
  68. /* set Rx FIFO size */
  69. usb_set_rxfifo(&udev->regs, RX_FIFO_FS_SIZE);
  70. /* set endpoint 0 to 3's Tx FIFO length and RAM address */
  71. for (i = 0U; i < USBFS_MAX_EP_COUNT; i++) {
  72. usb_set_txfifo(&udev->regs, i, USBFS_TX_FIFO_SIZE[i]);
  73. }
  74. }
  75. #endif /* USB_FS_CORE */
  76. /* make sure all FIFOs are flushed */
  77. /* flush all Tx FIFOs */
  78. (void)usb_txfifo_flush (&udev->regs, 0x10U);
  79. /* flush entire Rx FIFO */
  80. (void)usb_rxfifo_flush (&udev->regs);
  81. /* clear all pending device interrupts */
  82. udev->regs.dr->DIEPINTEN = 0U;
  83. udev->regs.dr->DOEPINTEN = 0U;
  84. udev->regs.dr->DAEPINT = 0xFFFFFFFFU;
  85. udev->regs.dr->DAEPINTEN = 0U;
  86. /* configure all IN/OUT endpoints */
  87. for (i = 0U; i < udev->bp.num_ep; i++) {
  88. if (udev->regs.er_in[i]->DIEPCTL & DEPCTL_EPEN) {
  89. udev->regs.er_in[i]->DIEPCTL |= DEPCTL_EPD | DEPCTL_SNAK;
  90. } else {
  91. udev->regs.er_in[i]->DIEPCTL = 0U;
  92. }
  93. /* set IN endpoint transfer length to 0 */
  94. udev->regs.er_in[i]->DIEPLEN = 0U;
  95. /* clear all pending IN endpoint interrupts */
  96. udev->regs.er_in[i]->DIEPINTF = 0xFFU;
  97. if (udev->regs.er_out[i]->DOEPCTL & DEPCTL_EPEN) {
  98. udev->regs.er_out[i]->DOEPCTL |= DEPCTL_EPD | DEPCTL_SNAK;
  99. } else {
  100. udev->regs.er_out[i]->DOEPCTL = 0U;
  101. }
  102. /* set OUT endpoint transfer length to 0 */
  103. udev->regs.er_out[i]->DOEPLEN = 0U;
  104. /* clear all pending OUT endpoint interrupts */
  105. udev->regs.er_out[i]->DOEPINTF = 0xFFU;
  106. }
  107. udev->regs.dr->DIEPINTEN |= DIEPINTEN_EPTXFUDEN;
  108. (void)usb_devint_enable (udev);
  109. return USB_OK;
  110. }
  111. /*!
  112. \brief enable the USB device mode interrupts
  113. \param[in] udev: pointer to USB device
  114. \param[out] none
  115. \retval operation status
  116. */
  117. usb_status usb_devint_enable (usb_core_driver *udev)
  118. {
  119. /* clear any pending USB OTG interrupts */
  120. udev->regs.gr->GOTGINTF = 0xFFFFFFFFU;
  121. /* clear any pending interrupts */
  122. udev->regs.gr->GINTF = 0xBFFFFFFFU;
  123. /* enable the USB wakeup and suspend interrupts */
  124. udev->regs.gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE;
  125. /* enable device_mode-related interrupts */
  126. if ((uint8_t)USB_USE_FIFO == udev->bp.transfer_mode) {
  127. udev->regs.gr->GINTEN |= GINTEN_RXFNEIE;
  128. }
  129. udev->regs.gr->GINTEN |= GINTEN_RSTIE | GINTEN_ENUMFIE | GINTEN_IEPIE |\
  130. GINTEN_OEPIE | GINTEN_SOFIE | GINTEN_ISOONCIE | GINTEN_ISOINCIE;
  131. #ifdef VBUS_SENSING_ENABLED
  132. udev->regs.gr->GINTEN |= GINTEN_SESIE | GINTEN_OTGIE;
  133. #endif /* VBUS_SENSING_ENABLED */
  134. return USB_OK;
  135. }
  136. /*!
  137. \brief active the USB endpoint0 transaction
  138. \param[in] udev: pointer to USB device
  139. \param[in] transc: the USB endpoint0 transaction
  140. \param[out] none
  141. \retval operation status
  142. */
  143. usb_status usb_transc0_active (usb_core_driver *udev, usb_transc *transc)
  144. {
  145. __IO uint32_t *reg_addr = NULL;
  146. uint8_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES;
  147. /* get the endpoint number */
  148. uint8_t ep_num = transc->ep_addr.num;
  149. if (ep_num) {
  150. /* not endpoint 0 */
  151. return USB_FAIL;
  152. }
  153. if (transc->ep_addr.dir) {
  154. reg_addr = &udev->regs.er_in[0]->DIEPCTL;
  155. } else {
  156. reg_addr = &udev->regs.er_out[0]->DOEPCTL;
  157. }
  158. /* endpoint 0 is activated after USB clock is enabled */
  159. *reg_addr &= ~(DEPCTL_MPL | DEPCTL_EPTYPE | DIEPCTL_TXFNUM);
  160. /* set endpoint 0 maximum packet length */
  161. *reg_addr |= EP0_MAXLEN[enum_speed];
  162. /* activate endpoint */
  163. *reg_addr |= ((uint32_t)transc->ep_type << 18U) | ((uint32_t)ep_num << 22U) | DEPCTL_SD0PID | DEPCTL_EPACT;
  164. return USB_OK;
  165. }
  166. /*!
  167. \brief active the USB transaction
  168. \param[in] udev: pointer to USB device
  169. \param[in] transc: the USB transaction
  170. \param[out] none
  171. \retval status
  172. */
  173. usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc)
  174. {
  175. __IO uint32_t *reg_addr = NULL;
  176. uint32_t epinten = 0U;
  177. uint8_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES;
  178. /* get the endpoint number */
  179. uint8_t ep_num = transc->ep_addr.num;
  180. /* enable endpoint interrupt number */
  181. if (transc->ep_addr.dir) {
  182. reg_addr = &udev->regs.er_in[ep_num]->DIEPCTL;
  183. epinten = 1U << ep_num;
  184. } else {
  185. reg_addr = &udev->regs.er_out[ep_num]->DOEPCTL;
  186. epinten = 1U << (16U + ep_num);
  187. }
  188. /* if the endpoint is not active, need change the endpoint control register */
  189. if (!(*reg_addr & DEPCTL_EPACT)) {
  190. *reg_addr &= ~(DEPCTL_MPL | DEPCTL_EPTYPE | DIEPCTL_TXFNUM);
  191. /* set endpoint maximum packet length */
  192. if (0U == ep_num) {
  193. *reg_addr |= EP0_MAXLEN[enum_speed];
  194. } else {
  195. *reg_addr |= transc->max_len;
  196. }
  197. /* activate endpoint */
  198. *reg_addr |= ((uint32_t)transc->ep_type << 18U) | ((uint32_t)ep_num << 22U) | DEPCTL_SD0PID | DEPCTL_EPACT;
  199. }
  200. /* enable the interrupts for this endpoint */
  201. udev->regs.dr->DAEPINTEN |= epinten;
  202. return USB_OK;
  203. }
  204. /*!
  205. \brief deactivate the USB transaction
  206. \param[in] udev: pointer to USB device
  207. \param[in] transc: the USB transaction
  208. \param[out] none
  209. \retval status
  210. */
  211. usb_status usb_transc_deactivate(usb_core_driver *udev, usb_transc *transc)
  212. {
  213. uint32_t epinten = 0U;
  214. uint8_t ep_num = transc->ep_addr.num;
  215. /* disable endpoint interrupt number */
  216. if (transc->ep_addr.dir) {
  217. epinten = 1U << ep_num;
  218. udev->regs.er_in[ep_num]->DIEPCTL &= ~DEPCTL_EPACT;
  219. } else {
  220. epinten = 1U << (ep_num + 16U);
  221. udev->regs.er_out[ep_num]->DOEPCTL &= ~DEPCTL_EPACT;
  222. }
  223. /* disable the interrupts for this endpoint */
  224. udev->regs.dr->DAEPINTEN &= ~epinten;
  225. return USB_OK;
  226. }
  227. /*!
  228. \brief configure USB transaction to start IN transfer
  229. \param[in] udev: pointer to USB device
  230. \param[in] transc: the USB IN transaction
  231. \param[out] none
  232. \retval operation status
  233. */
  234. usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc)
  235. {
  236. usb_status status = USB_OK;
  237. uint8_t ep_num = transc->ep_addr.num;
  238. __IO uint32_t epctl = udev->regs.er_in[ep_num]->DIEPCTL;
  239. __IO uint32_t eplen = udev->regs.er_in[ep_num]->DIEPLEN;
  240. eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT);
  241. /* zero length packet or endpoint 0 */
  242. if (0U == transc->xfer_len) {
  243. /* set transfer packet count to 1 */
  244. eplen |= 1U << 19U;
  245. } else {
  246. /* set transfer packet count */
  247. if (0U == ep_num) {
  248. transc->xfer_len = USB_MIN(transc->xfer_len, transc->max_len);
  249. eplen |= 1U << 19U;
  250. } else {
  251. eplen |= (((transc->xfer_len - 1U) + transc->max_len) / transc->max_len) << 19U;
  252. }
  253. /* set endpoint transfer length */
  254. eplen |= transc->xfer_len;
  255. if (transc->ep_type == (uint8_t)USB_EPTYPE_ISOC) {
  256. eplen |= DIEPLEN_MCNT & (1U << 29U);
  257. }
  258. }
  259. udev->regs.er_in[ep_num]->DIEPLEN = eplen;
  260. if (transc->ep_type == (uint8_t)USB_EPTYPE_ISOC) {
  261. if (((udev->regs.dr->DSTAT & DSTAT_FNRSOF) >> 8U) & 0x01U) {
  262. epctl |= DEPCTL_SEVNFRM;
  263. } else {
  264. epctl |= DEPCTL_SODDFRM;
  265. }
  266. }
  267. /* enable the endpoint and clear the NAK */
  268. epctl |= DEPCTL_CNAK | DEPCTL_EPEN;
  269. udev->regs.er_in[ep_num]->DIEPCTL = epctl;
  270. if ((uint8_t)USB_USE_FIFO == udev->bp.transfer_mode) {
  271. if (transc->ep_type != (uint8_t)USB_EPTYPE_ISOC) {
  272. /* enable the Tx FIFO empty interrupt for this endpoint */
  273. if (transc->xfer_len > 0U) {
  274. udev->regs.dr->DIEPFEINTEN |= 1U << ep_num;
  275. }
  276. } else {
  277. (void)usb_txfifo_write (&udev->regs, transc->xfer_buf, ep_num, (uint16_t)transc->xfer_len);
  278. }
  279. }
  280. return status;
  281. }
  282. /*!
  283. \brief configure usb transaction to start OUT transfer
  284. \param[in] udev: pointer to usb device
  285. \param[in] transc: the usb OUT transaction
  286. \param[out] none
  287. \retval status
  288. */
  289. usb_status usb_transc_outxfer (usb_core_driver *udev, usb_transc *transc)
  290. {
  291. usb_status status = USB_OK;
  292. uint8_t ep_num = transc->ep_addr.num;
  293. uint32_t epctl = udev->regs.er_out[ep_num]->DOEPCTL;
  294. uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN;
  295. eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT);
  296. /* zero length packet or endpoint 0 */
  297. if ((0U == transc->xfer_len) || (0U == ep_num)) {
  298. /* set the transfer length to max packet size */
  299. eplen |= transc->max_len;
  300. /* set the transfer packet count to 1 */
  301. eplen |= 1U << 19U;
  302. } else {
  303. /* configure the transfer size and packet count as follows:
  304. * pktcnt = N
  305. * xfersize = N * maxpacket
  306. */
  307. uint32_t packet_count = (transc->xfer_len + transc->max_len - 1U) / transc->max_len;
  308. eplen |= packet_count << 19U;
  309. eplen |= packet_count * transc->max_len;
  310. }
  311. udev->regs.er_out[ep_num]->DOEPLEN = eplen;
  312. if (transc->ep_type == (uint8_t)USB_EPTYPE_ISOC) {
  313. if (transc->frame_num) {
  314. epctl |= DEPCTL_SD1PID;
  315. } else {
  316. epctl |= DEPCTL_SD0PID;
  317. }
  318. }
  319. /* enable the endpoint and clear the NAK */
  320. epctl |= DEPCTL_EPEN | DEPCTL_CNAK;
  321. udev->regs.er_out[ep_num]->DOEPCTL = epctl;
  322. return status;
  323. }
  324. /*!
  325. \brief set the USB transaction STALL status
  326. \param[in] udev: pointer to USB device
  327. \param[in] transc: the USB transaction
  328. \param[out] none
  329. \retval status
  330. */
  331. usb_status usb_transc_stall (usb_core_driver *udev, usb_transc *transc)
  332. {
  333. __IO uint32_t *reg_addr = NULL;
  334. uint8_t ep_num = transc->ep_addr.num;
  335. if (transc->ep_addr.dir) {
  336. reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL);
  337. /* set the endpoint disable bit */
  338. if (*reg_addr & DEPCTL_EPEN) {
  339. *reg_addr |= DEPCTL_EPD;
  340. }
  341. } else {
  342. /* set the endpoint stall bit */
  343. reg_addr = &(udev->regs.er_out[ep_num]->DOEPCTL);
  344. }
  345. /* set the endpoint stall bit */
  346. *reg_addr |= DEPCTL_STALL;
  347. return USB_OK;
  348. }
  349. /*!
  350. \brief clear the USB transaction STALL status
  351. \param[in] udev: pointer to USB device
  352. \param[in] transc: the USB transaction
  353. \param[out] none
  354. \retval operation status
  355. */
  356. usb_status usb_transc_clrstall(usb_core_driver *udev, usb_transc *transc)
  357. {
  358. __IO uint32_t *reg_addr = NULL;
  359. uint8_t ep_num = transc->ep_addr.num;
  360. if (transc->ep_addr.dir) {
  361. reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL);
  362. } else {
  363. reg_addr = &(udev->regs.er_out[ep_num]->DOEPCTL);
  364. }
  365. /* clear the endpoint stall bits */
  366. *reg_addr &= ~DEPCTL_STALL;
  367. /* reset data PID of the periodic endpoints */
  368. if ((transc->ep_type == (uint8_t)USB_EPTYPE_INTR) || (transc->ep_type == (uint8_t)USB_EPTYPE_BULK)) {
  369. *reg_addr |= DEPCTL_SD0PID;
  370. }
  371. return USB_OK;
  372. }
  373. /*!
  374. \brief read device IN endpoint interrupt flag register
  375. \param[in] udev: pointer to USB device
  376. \param[in] ep_num: endpoint number
  377. \param[out] none
  378. \retval interrupt value
  379. */
  380. uint32_t usb_iepintr_read (usb_core_driver *udev, uint8_t ep_num)
  381. {
  382. uint32_t value = 0U, fifoemptymask, commonintmask;
  383. commonintmask = udev->regs.dr->DIEPINTEN;
  384. fifoemptymask = udev->regs.dr->DIEPFEINTEN;
  385. /* check FIFO empty interrupt enable bit */
  386. commonintmask |= ((fifoemptymask >> ep_num) & 0x1U) << 7;
  387. value = udev->regs.er_in[ep_num]->DIEPINTF & commonintmask;
  388. return value;
  389. }
  390. /*!
  391. \brief configures OUT endpoint 0 to receive SETUP packets
  392. \param[in] udev: pointer to USB device
  393. \param[out] none
  394. \retval none
  395. */
  396. void usb_ctlep_startout (usb_core_driver *udev)
  397. {
  398. /* set OUT endpoint 0 receive length to 24 bytes, 1 packet and 3 setup packets */
  399. udev->regs.er_out[0]->DOEPLEN = DOEP0_TLEN(8U * 3U) | DOEP0_PCNT(1U) | DOEP0_STPCNT(3U);
  400. }
  401. /*!
  402. \brief active remote wakeup signaling
  403. \param[in] udev: pointer to USB device
  404. \param[out] none
  405. \retval none
  406. */
  407. void usb_rwkup_active (usb_core_driver *udev)
  408. {
  409. if (udev->dev.pm.dev_remote_wakeup) {
  410. if (udev->regs.dr->DSTAT & DSTAT_SPST) {
  411. if (udev->bp.low_power) {
  412. /* ungate USB core clock */
  413. *udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK);
  414. }
  415. /* active remote wakeup signaling */
  416. udev->regs.dr->DCTL |= DCTL_RWKUP;
  417. usb_mdelay(5U);
  418. udev->regs.dr->DCTL &= ~DCTL_RWKUP;
  419. }
  420. }
  421. }
  422. /*!
  423. \brief active USB core clock
  424. \param[in] udev: pointer to USB device
  425. \param[out] none
  426. \retval none
  427. */
  428. void usb_clock_active (usb_core_driver *udev)
  429. {
  430. if (udev->bp.low_power) {
  431. if (udev->regs.dr->DSTAT & DSTAT_SPST) {
  432. /* un-gate USB Core clock */
  433. *udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK);
  434. }
  435. }
  436. }
  437. /*!
  438. \brief USB device suspend
  439. \param[in] udev: pointer to USB device
  440. \param[out] none
  441. \retval none
  442. */
  443. void usb_dev_suspend (usb_core_driver *udev)
  444. {
  445. __IO uint32_t devstat = udev->regs.dr->DSTAT;
  446. if ((udev->bp.low_power) && (devstat & DSTAT_SPST)) {
  447. /* switch-off the USB clocks */
  448. *udev->regs.PWRCLKCTL |= PWRCLKCTL_SHCLK;
  449. /* enter DEEP_SLEEP mode with LDO in low power mode */
  450. pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, PMU_LOWDRIVER_DISABLE, WFI_CMD);
  451. }
  452. }
  453. /*!
  454. \brief stop the device and clean up FIFOs
  455. \param[in] udev: pointer to USB device
  456. \param[out] none
  457. \retval none
  458. */
  459. void usb_dev_stop (usb_core_driver *udev)
  460. {
  461. uint32_t i;
  462. udev->dev.cur_status = 1U;
  463. /* clear all interrupt flag and enable bits */
  464. for (i = 0U; i < udev->bp.num_ep; i++) {
  465. udev->regs.er_in[i]->DIEPINTF = 0xFFU;
  466. udev->regs.er_out[i]->DOEPINTF = 0xFFU;
  467. }
  468. udev->regs.dr->DIEPINTEN = 0U;
  469. udev->regs.dr->DOEPINTEN = 0U;
  470. udev->regs.dr->DAEPINTEN = 0U;
  471. udev->regs.dr->DAEPINT = 0xFFFFFFFFU;
  472. /* flush the FIFO */
  473. (void)usb_rxfifo_flush (&udev->regs);
  474. (void)usb_txfifo_flush (&udev->regs, 0x10U);
  475. }