gd32f30x_adc.c 35 KB

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  1. /*!
  2. \file gd32f30x_adc.c
  3. \brief ADC driver
  4. \version 2023-12-30, V2.2.0, firmware for GD32F30x
  5. */
  6. /*
  7. Copyright (c) 2020, GigaDevice Semiconductor Inc.
  8. Redistribution and use in source and binary forms, with or without modification,
  9. are permitted provided that the following conditions are met:
  10. 1. Redistributions of source code must retain the above copyright notice, this
  11. list of conditions and the following disclaimer.
  12. 2. Redistributions in binary form must reproduce the above copyright notice,
  13. this list of conditions and the following disclaimer in the documentation
  14. and/or other materials provided with the distribution.
  15. 3. Neither the name of the copyright holder nor the names of its contributors
  16. may be used to endorse or promote products derived from this software without
  17. specific prior written permission.
  18. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  19. AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  20. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  22. INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23. NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  24. PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  25. WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  26. ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  27. OF SUCH DAMAGE.
  28. */
  29. #include "gd32f30x_adc.h"
  30. /*!
  31. \brief reset ADC
  32. \param[in] adc_periph: ADCx,x=0,1,2
  33. only one among these parameters can be selected
  34. \param[out] none
  35. \retval none
  36. */
  37. void adc_deinit(uint32_t adc_periph)
  38. {
  39. switch(adc_periph){
  40. case ADC0:
  41. rcu_periph_reset_enable(RCU_ADC0RST);
  42. rcu_periph_reset_disable(RCU_ADC0RST);
  43. break;
  44. case ADC1:
  45. rcu_periph_reset_enable(RCU_ADC1RST);
  46. rcu_periph_reset_disable(RCU_ADC1RST);
  47. break;
  48. #if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
  49. case ADC2:
  50. rcu_periph_reset_enable(RCU_ADC2RST);
  51. rcu_periph_reset_disable(RCU_ADC2RST);
  52. break;
  53. #endif
  54. default:
  55. break;
  56. }
  57. }
  58. /*!
  59. \brief enable ADC interface
  60. \param[in] adc_periph: ADCx,x=0,1,2
  61. only one among these parameters can be selected
  62. \param[out] none
  63. \retval none
  64. */
  65. void adc_enable(uint32_t adc_periph)
  66. {
  67. if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){
  68. ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON;
  69. }
  70. }
  71. /*!
  72. \brief disable ADC interface
  73. \param[in] adc_periph: ADCx,x=0,1,2
  74. only one among these parameters can be selected
  75. \param[out] none
  76. \retval none
  77. */
  78. void adc_disable(uint32_t adc_periph)
  79. {
  80. ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON);
  81. }
  82. /*!
  83. \brief ADC calibration and reset calibration
  84. \param[in] adc_periph: ADCx,x=0,1,2
  85. only one among these parameters can be selected
  86. \param[out] none
  87. \retval none
  88. */
  89. void adc_calibration_enable(uint32_t adc_periph)
  90. {
  91. /* reset the selected ADC calibration registers */
  92. ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB;
  93. /* check the RSTCLB bit state */
  94. while((ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){
  95. }
  96. /* enable ADC calibration process */
  97. ADC_CTL1(adc_periph) |= ADC_CTL1_CLB;
  98. /* check the CLB bit state */
  99. while((ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){
  100. }
  101. }
  102. /*!
  103. \brief enable DMA request
  104. \param[in] adc_periph: ADCx,x=0,1,2
  105. only one among these parameters can be selected
  106. \param[out] none
  107. \retval none
  108. */
  109. void adc_dma_mode_enable(uint32_t adc_periph)
  110. {
  111. ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA);
  112. }
  113. /*!
  114. \brief disable DMA request
  115. \param[in] adc_periph: ADCx,x=0,1,2
  116. only one among these parameters can be selected
  117. \param[out] none
  118. \retval none
  119. */
  120. void adc_dma_mode_disable(uint32_t adc_periph)
  121. {
  122. ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA);
  123. }
  124. /*!
  125. \brief enable the temperature sensor and Vrefint channel
  126. \param[in] none
  127. \param[out] none
  128. \retval none
  129. */
  130. void adc_tempsensor_vrefint_enable(void)
  131. {
  132. /* enable the temperature sensor and Vrefint channel */
  133. ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN;
  134. }
  135. /*!
  136. \brief disable the temperature sensor and Vrefint channel
  137. \param[in] none
  138. \param[out] none
  139. \retval none
  140. */
  141. void adc_tempsensor_vrefint_disable(void)
  142. {
  143. /* disable the temperature sensor and Vrefint channel */
  144. ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN;
  145. }
  146. /*!
  147. \brief configure ADC resolution
  148. \param[in] adc_periph: ADCx,x=0,1,2
  149. only one among these parameters can be selected
  150. \param[in] resolution: ADC resolution
  151. only one among these parameters can be selected
  152. \arg ADC_RESOLUTION_12B: 12-bit ADC resolution
  153. \arg ADC_RESOLUTION_10B: 10-bit ADC resolution
  154. \arg ADC_RESOLUTION_8B: 8-bit ADC resolution
  155. \arg ADC_RESOLUTION_6B: 6-bit ADC resolution
  156. \param[out] none
  157. \retval none
  158. */
  159. void adc_resolution_config(uint32_t adc_periph , uint32_t resolution)
  160. {
  161. ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_DRES);
  162. ADC_OVSAMPCTL(adc_periph) |= (uint32_t)resolution;
  163. }
  164. /*!
  165. \brief configure ADC discontinuous mode
  166. \param[in] adc_periph: ADCx,x=0,1,2
  167. only one among these parameters can be selected
  168. \param[in] adc_channel_group: select the channel group
  169. only one among these parameters can be selected
  170. \arg ADC_REGULAR_CHANNEL: regular channel group
  171. \arg ADC_INSERTED_CHANNEL: inserted channel group
  172. \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel
  173. \param[in] length: number of conversions in discontinuous mode,the number can be 1..8
  174. for regular channel ,the number has no effect for inserted channel
  175. \param[out] none
  176. \retval none
  177. */
  178. void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length)
  179. {
  180. ADC_CTL0(adc_periph) &= ~((uint32_t)( ADC_CTL0_DISRC | ADC_CTL0_DISIC ));
  181. switch(adc_channel_group){
  182. case ADC_REGULAR_CHANNEL:
  183. /* config the number of conversions in discontinuous mode */
  184. ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM);
  185. ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - 1U));
  186. ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC;
  187. break;
  188. case ADC_INSERTED_CHANNEL:
  189. ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC;
  190. break;
  191. case ADC_CHANNEL_DISCON_DISABLE:
  192. default:
  193. break;
  194. }
  195. }
  196. /*!
  197. \brief configure the ADC sync mode
  198. \param[in] mode: ADC mode
  199. only one among these parameters can be selected
  200. \arg ADC_MODE_FREE: all the ADCs work independently
  201. \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode
  202. \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode
  203. \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode
  204. \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode
  205. \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only
  206. \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only
  207. \arg ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only
  208. \arg ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only
  209. \arg ADC_DAUL_INSERTED_TRRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only
  210. \param[out] none
  211. \retval none
  212. */
  213. void adc_mode_config(uint32_t mode)
  214. {
  215. ADC_CTL0(ADC0) &= ~(ADC_CTL0_SYNCM);
  216. ADC_CTL0(ADC0) |= mode;
  217. }
  218. /*!
  219. \brief enable or disable ADC special function
  220. \param[in] adc_periph: ADCx,x=0,1,2
  221. only one among these parameters can be selected
  222. \param[in] function: the function to config
  223. one or more parameters can be selected below
  224. \arg ADC_SCAN_MODE: scan mode select
  225. \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically
  226. \arg ADC_CONTINUOUS_MODE: continuous mode select
  227. \param[in] newvalue: ENABLE or DISABLE
  228. \param[out] none
  229. \retval none
  230. */
  231. void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue)
  232. {
  233. if(newvalue){
  234. if(0U != (function & ADC_SCAN_MODE)){
  235. ADC_CTL0(adc_periph) |= ADC_SCAN_MODE;
  236. }
  237. if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
  238. ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO;
  239. }
  240. if(0U != (function & ADC_CONTINUOUS_MODE)){
  241. ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE;
  242. }
  243. }else{
  244. if(0U != (function & ADC_SCAN_MODE)){
  245. ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE;
  246. }
  247. if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
  248. ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO;
  249. }
  250. if(0U != (function & ADC_CONTINUOUS_MODE)){
  251. ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE;
  252. }
  253. }
  254. }
  255. /*!
  256. \brief configure ADC data alignment
  257. \param[in] adc_periph: ADCx,x=0,1,2
  258. only one among these parameters can be selected
  259. \param[in] data_alignment: data alignment select
  260. only one parameter can be selected
  261. \arg ADC_DATAALIGN_RIGHT: LSB alignment
  262. \arg ADC_DATAALIGN_LEFT: MSB alignment
  263. \param[out] none
  264. \retval none
  265. */
  266. void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment)
  267. {
  268. if(ADC_DATAALIGN_RIGHT != data_alignment){
  269. ADC_CTL1(adc_periph) |= ADC_CTL1_DAL;
  270. }else{
  271. ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL);
  272. }
  273. }
  274. /*!
  275. \brief configure the length of regular channel group or inserted channel group
  276. \param[in] adc_periph: ADCx,x=0,1,2
  277. only one among these parameters can be selected
  278. \param[in] adc_channel_group: select the channel group
  279. only one parameter can be selected
  280. \arg ADC_REGULAR_CHANNEL: regular channel group
  281. \arg ADC_INSERTED_CHANNEL: inserted channel group
  282. \param[in] length: the length of the channel
  283. regular channel 1-16
  284. inserted channel 1-4
  285. \param[out] none
  286. \retval none
  287. */
  288. void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length)
  289. {
  290. switch(adc_channel_group){
  291. case ADC_REGULAR_CHANNEL:
  292. ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL);
  293. ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-1U));
  294. break;
  295. case ADC_INSERTED_CHANNEL:
  296. ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL);
  297. ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-1U));
  298. break;
  299. default:
  300. break;
  301. }
  302. }
  303. /*!
  304. \brief configure ADC regular channel
  305. \param[in] adc_periph: ADCx,x=0,1,2
  306. only one among these parameters can be selected
  307. \param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15
  308. \param[in] adc_channel: the selected ADC channel
  309. only one among these parameters can be selected
  310. \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx
  311. \param[in] sample_time: the sample time value
  312. only one parameter can be selected
  313. \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles
  314. \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles
  315. \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles
  316. \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles
  317. \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles
  318. \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
  319. \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles
  320. \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles
  321. \param[out] none
  322. \retval none
  323. */
  324. void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time)
  325. {
  326. uint32_t rsq,sampt;
  327. /* ADC regular sequence config */
  328. if(rank < 6U){
  329. rsq = ADC_RSQ2(adc_periph);
  330. rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*rank)));
  331. rsq |= ((uint32_t)adc_channel << (5U*rank));
  332. ADC_RSQ2(adc_periph) = rsq;
  333. }else if(rank < 12U){
  334. rsq = ADC_RSQ1(adc_periph);
  335. rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-6U))));
  336. rsq |= ((uint32_t)adc_channel << (5U*(rank-6U)));
  337. ADC_RSQ1(adc_periph) = rsq;
  338. }else if(rank < 16U){
  339. rsq = ADC_RSQ0(adc_periph);
  340. rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-12U))));
  341. rsq |= ((uint32_t)adc_channel << (5U*(rank-12U)));
  342. ADC_RSQ0(adc_periph) = rsq;
  343. }else{
  344. }
  345. /* ADC sampling time config */
  346. if(adc_channel < 10U){
  347. sampt = ADC_SAMPT1(adc_periph);
  348. sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel)));
  349. sampt |= (uint32_t)(sample_time << (3U*adc_channel));
  350. ADC_SAMPT1(adc_periph) = sampt;
  351. }else if(adc_channel < 18U){
  352. sampt = ADC_SAMPT0(adc_periph);
  353. sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U))));
  354. sampt |= (uint32_t)(sample_time << (3U*(adc_channel-10U)));
  355. ADC_SAMPT0(adc_periph) = sampt;
  356. }else{
  357. }
  358. }
  359. /*!
  360. \brief configure ADC inserted channel
  361. \param[in] adc_periph: ADCx,x=0,1,2
  362. only one among these parameters can be selected
  363. \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3
  364. \param[in] adc_channel: the selected ADC channel
  365. only one among these parameters can be selected
  366. \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx
  367. \param[in] sample_time: The sample time value
  368. only one parameter can be selected
  369. \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles
  370. \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles
  371. \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles
  372. \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles
  373. \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles
  374. \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
  375. \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles
  376. \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles
  377. \param[out] none
  378. \retval none
  379. */
  380. void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time)
  381. {
  382. uint8_t inserted_length;
  383. uint32_t isq,sampt;
  384. inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
  385. isq = ADC_ISQ(adc_periph);
  386. isq &= ~((uint32_t)(ADC_ISQ_ISQN << (5U * ((3 + rank) - inserted_length))));
  387. isq |= ((uint32_t)adc_channel << (5U * ((3 + rank) - inserted_length)));
  388. ADC_ISQ(adc_periph) = isq;
  389. /* ADC sampling time config */
  390. if(adc_channel < 10U){
  391. sampt = ADC_SAMPT1(adc_periph);
  392. sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel)));
  393. sampt |= (uint32_t) sample_time << (3U*adc_channel);
  394. ADC_SAMPT1(adc_periph) = sampt;
  395. }else if(adc_channel < 18U){
  396. sampt = ADC_SAMPT0(adc_periph);
  397. sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U))));
  398. sampt |= ((uint32_t)sample_time << (3U*(adc_channel-10U)));
  399. ADC_SAMPT0(adc_periph) = sampt;
  400. }else{
  401. }
  402. }
  403. /*!
  404. \brief configure ADC inserted channel offset
  405. \param[in] adc_periph: ADCx,x=0,1,2
  406. only one among these parameters can be selected
  407. \param[in] inserted_channel : insert channel select
  408. only one parameter can be selected
  409. \arg ADC_INSERTED_CHANNEL_0: inserted channel0
  410. \arg ADC_INSERTED_CHANNEL_1: inserted channel1
  411. \arg ADC_INSERTED_CHANNEL_2: inserted channel2
  412. \arg ADC_INSERTED_CHANNEL_3: inserted channel3
  413. \param[in] offset : the offset data
  414. \param[out] none
  415. \retval none
  416. */
  417. void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset)
  418. {
  419. uint8_t inserted_length;
  420. uint32_t num = 0U;
  421. inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
  422. num = 3U - (inserted_length - inserted_channel);
  423. if(num <= 3U){
  424. /* calculate the offset of the register */
  425. num = num * 4U;
  426. /* config the offset of the selected channels */
  427. REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset);
  428. }
  429. }
  430. /*!
  431. \brief enable ADC external trigger
  432. \param[in] adc_periph: ADCx,x=0,1,2
  433. only one among these parameters can be selected
  434. \param[in] adc_channel_group: select the channel group
  435. one or more parameters can be selected
  436. \arg ADC_REGULAR_CHANNEL: regular channel group
  437. \arg ADC_INSERTED_CHANNEL: inserted channel group
  438. \param[in] newvalue: ENABLE or DISABLE
  439. \param[out] none
  440. \retval none
  441. */
  442. void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue)
  443. {
  444. if(newvalue){
  445. if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
  446. ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC;
  447. }
  448. if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
  449. ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC;
  450. }
  451. }else{
  452. if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
  453. ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC;
  454. }
  455. if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
  456. ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC;
  457. }
  458. }
  459. }
  460. /*!
  461. \brief configure ADC external trigger source
  462. \param[in] adc_periph: ADCx,x=0,1,2
  463. only one among these parameters can be selected
  464. \param[in] adc_channel_group: select the channel group
  465. only one parameter can be selected
  466. \arg ADC_REGULAR_CHANNEL: regular channel group
  467. \arg ADC_INSERTED_CHANNEL: inserted channel group
  468. \param[in] external_trigger_source: regular or inserted group trigger source
  469. only one parameter can be selected
  470. for regular channel:
  471. \arg ADC0_1_EXTTRIG_REGULAR_T0_CH0: timer 0 CC0 event select
  472. \arg ADC0_1_EXTTRIG_REGULAR_T0_CH1: timer 0 CC1 event select
  473. \arg ADC0_1_EXTTRIG_REGULAR_T0_CH2: timer 0 CC2 event select
  474. \arg ADC0_1_EXTTRIG_REGULAR_T1_CH1: timer 1 CC1 event select
  475. \arg ADC0_1_EXTTRIG_REGULAR_T2_TRGO: timer 2 TRGO event select
  476. \arg ADC0_1_EXTTRIG_REGULAR_T3_CH3: timer 3 CC3 event select
  477. \arg ADC0_1_EXTTRIG_REGULAR_T7_TRGO: timer 7 TRGO event select
  478. \arg ADC0_1_EXTTRIG_REGULAR_EXTI_11 : external interrupt line 11
  479. \arg ADC2_EXTTRIG_REGULAR_T2_CH0: timer 2 CC0 event select
  480. \arg ADC2_EXTTRIG_REGULAR_T1_CH2: timer 1 CC2 event select
  481. \arg ADC2_EXTTRIG_REGULAR_T0_CH2: timer 0 CC2 event select
  482. \arg ADC2_EXTTRIG_REGULAR_T7_CH0: timer 7 CC0 event select
  483. \arg ADC2_EXTTRIG_REGULAR_T7_TRGO: timer 7 TRGO event select
  484. \arg ADC2_EXTTRIG_REGULAR_T4_CH0: timer 4 CC0 event select
  485. \arg ADC2_EXTTRIG_REGULAR_T4_CH2: timer 4 CC2 event select
  486. \arg ADC0_1_2_EXTTRIG_REGULAR_NONE: software trigger
  487. for inserted channel:
  488. \arg ADC0_1_EXTTRIG_INSERTED_T0_TRGO: timer 0 TRGO event select
  489. \arg ADC0_1_EXTTRIG_INSERTED_T0_CH3: timer 0 CC3 event select
  490. \arg ADC0_1_EXTTRIG_INSERTED_T1_TRGO: timer 1 TRGO event select
  491. \arg ADC0_1_EXTTRIG_INSERTED_T1_CH0: timer 1 CC0 event select
  492. \arg ADC0_1_EXTTRIG_INSERTED_T2_CH3: timer 2 CC3 event select
  493. \arg ADC0_1_EXTTRIG_INSERTED_T3_TRGO: timer 3 TRGO event select
  494. \arg ADC0_1_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15
  495. \arg ADC0_1_EXTTRIG_INSERTED_T7_CH3: timer 7 CC3 event select
  496. \arg ADC2_EXTTRIG_INSERTED_T0_TRGO: timer 0 TRGO event select
  497. \arg ADC2_EXTTRIG_INSERTED_T0_CH3: timer 0 CC3 event select
  498. \arg ADC2_EXTTRIG_INSERTED_T3_CH2: timer 3 CC2 event select
  499. \arg ADC2_EXTTRIG_INSERTED_T7_CH1: timer 7 CC1 event select
  500. \arg ADC2_EXTTRIG_INSERTED_T7_CH3: timer 7 CC3 event select
  501. \arg ADC2_EXTTRIG_INSERTED_T4_TRGO: timer 4 TRGO event select
  502. \arg ADC2_EXTTRIG_INSERTED_T4_CH3: timer 4 CC3 event select
  503. \arg ADC0_1_2_EXTTRIG_INSERTED_NONE: software trigger
  504. \param[out] none
  505. \retval none
  506. */
  507. void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source)
  508. {
  509. switch(adc_channel_group){
  510. case ADC_REGULAR_CHANNEL:
  511. ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC);
  512. ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
  513. break;
  514. case ADC_INSERTED_CHANNEL:
  515. ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC);
  516. ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
  517. break;
  518. default:
  519. break;
  520. }
  521. }
  522. /*!
  523. \brief enable ADC software trigger
  524. \param[in] adc_periph: ADCx,x=0,1,2
  525. only one among these parameters can be selected
  526. \param[in] adc_channel_group: select the channel group
  527. one or more parameters can be selected
  528. \arg ADC_REGULAR_CHANNEL: regular channel group
  529. \arg ADC_INSERTED_CHANNEL: inserted channel group
  530. \param[out] none
  531. \retval none
  532. */
  533. void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group)
  534. {
  535. if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
  536. ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST;
  537. }
  538. if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
  539. ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST;
  540. }
  541. }
  542. /*!
  543. \brief read ADC regular group data register
  544. \param[in] adc_periph: ADCx,x=0,1,2
  545. only one among these parameters can be selected
  546. \param[in] none
  547. \param[out] none
  548. \retval the conversion value
  549. */
  550. uint16_t adc_regular_data_read(uint32_t adc_periph)
  551. {
  552. return (uint16_t)(ADC_RDATA(adc_periph));
  553. }
  554. /*!
  555. \brief read ADC inserted group data register
  556. \param[in] adc_periph: ADCx,x=0,1,2
  557. only one among these parameters can be selected
  558. \param[in] inserted_channel : insert channel select
  559. only one parameter can be selected
  560. \arg ADC_INSERTED_CHANNEL_0: inserted Channel0
  561. \arg ADC_INSERTED_CHANNEL_1: inserted channel1
  562. \arg ADC_INSERTED_CHANNEL_2: inserted Channel2
  563. \arg ADC_INSERTED_CHANNEL_3: inserted Channel3
  564. \param[out] none
  565. \retval the conversion value
  566. */
  567. uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel)
  568. {
  569. uint32_t idata;
  570. /* read the data of the selected channel */
  571. switch(inserted_channel){
  572. case ADC_INSERTED_CHANNEL_0:
  573. idata = ADC_IDATA0(adc_periph);
  574. break;
  575. case ADC_INSERTED_CHANNEL_1:
  576. idata = ADC_IDATA1(adc_periph);
  577. break;
  578. case ADC_INSERTED_CHANNEL_2:
  579. idata = ADC_IDATA2(adc_periph);
  580. break;
  581. case ADC_INSERTED_CHANNEL_3:
  582. idata = ADC_IDATA3(adc_periph);
  583. break;
  584. default:
  585. idata = 0U;
  586. break;
  587. }
  588. return (uint16_t)idata;
  589. }
  590. /*!
  591. \brief read the last ADC0 and ADC1 conversion result data in sync mode
  592. \param[in] none
  593. \param[out] none
  594. \retval the conversion value
  595. */
  596. uint32_t adc_sync_mode_convert_value_read(void)
  597. {
  598. /* return conversion value */
  599. return ADC_RDATA(ADC0);
  600. }
  601. /*!
  602. \brief get the ADC flag bits
  603. \param[in] adc_periph: ADCx,x=0,1,2
  604. only one among these parameters can be selected
  605. \param[in] adc_flag: the adc flag bits
  606. only one parameter can be selected
  607. \arg ADC_FLAG_WDE: analog watchdog event flag
  608. \arg ADC_FLAG_EOC: end of group conversion flag
  609. \arg ADC_FLAG_EOIC: end of inserted group conversion flag
  610. \arg ADC_FLAG_STIC: start flag of inserted channel group
  611. \arg ADC_FLAG_STRC: start flag of regular channel group
  612. \param[out] none
  613. \retval FlagStatus: SET or RESET
  614. */
  615. FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag)
  616. {
  617. FlagStatus reval = RESET;
  618. if(ADC_STAT(adc_periph) & adc_flag){
  619. reval = SET;
  620. }
  621. return reval;
  622. }
  623. /*!
  624. \brief clear the ADC flag bits
  625. \param[in] adc_periph: ADCx,x=0,1,2
  626. only one among these parameters can be selected
  627. \param[in] adc_flag: the adc flag bits
  628. one or more parameters can be selected
  629. \arg ADC_FLAG_WDE: analog watchdog event flag
  630. \arg ADC_FLAG_EOC: end of group conversion flag
  631. \arg ADC_FLAG_EOIC: end of inserted group conversion flag
  632. \arg ADC_FLAG_STIC: start flag of inserted channel group
  633. \arg ADC_FLAG_STRC: start flag of regular channel group
  634. \param[out] none
  635. \retval none
  636. */
  637. void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag)
  638. {
  639. ADC_STAT(adc_periph) = ~((uint32_t)adc_flag);
  640. }
  641. /*!
  642. \brief get the ADC interrupt bits
  643. \param[in] adc_periph: ADCx,x=0,1,2
  644. only one among these parameters can be selected
  645. \param[in] adc_interrupt: the adc interrupt bits
  646. only oneparameter can be selected
  647. \arg ADC_INT_FLAG_WDE: analog watchdog interrupt
  648. \arg ADC_INT_FLAG_EOC: end of group conversion interrupt
  649. \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt
  650. \param[out] none
  651. \retval FlagStatus: SET or RESET
  652. */
  653. FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt)
  654. {
  655. FlagStatus interrupt_flag = RESET;
  656. uint32_t state;
  657. /* check the interrupt bits */
  658. switch(adc_interrupt){
  659. case ADC_INT_FLAG_WDE:
  660. state = ADC_STAT(adc_periph) & ADC_STAT_WDE;
  661. if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){
  662. interrupt_flag = SET;
  663. }
  664. break;
  665. case ADC_INT_FLAG_EOC:
  666. state = ADC_STAT(adc_periph) & ADC_STAT_EOC;
  667. if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){
  668. interrupt_flag = SET;
  669. }
  670. break;
  671. case ADC_INT_FLAG_EOIC:
  672. state = ADC_STAT(adc_periph) & ADC_STAT_EOIC;
  673. if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){
  674. interrupt_flag = SET;
  675. }
  676. break;
  677. default:
  678. break;
  679. }
  680. return interrupt_flag;
  681. }
  682. /*!
  683. \brief clear the ADC flag
  684. \param[in] adc_periph: ADCx,x=0,1,2
  685. only one among these parameters can be selected
  686. \param[in] adc_interrupt: the adc status flag
  687. one or more parameters can be selected
  688. \arg ADC_INT_FLAG_WDE: analog watchdog interrupt
  689. \arg ADC_INT_FLAG_EOC: end of group conversion interrupt
  690. \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt
  691. \param[out] none
  692. \retval none
  693. */
  694. void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt)
  695. {
  696. ADC_STAT(adc_periph) = ~((uint32_t)adc_interrupt);
  697. }
  698. /*!
  699. \brief enable ADC interrupt
  700. \param[in] adc_periph: ADCx,x=0,1,2
  701. only one among these parameters can be selected
  702. \param[in] adc_interrupt: the adc interrupt
  703. one or more parameters can be selected
  704. \arg ADC_INT_WDE: analog watchdog interrupt flag
  705. \arg ADC_INT_EOC: end of group conversion interrupt flag
  706. \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag
  707. \param[out] none
  708. \retval none
  709. */
  710. void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt)
  711. {
  712. if(0U != (adc_interrupt & ADC_INT_WDE)){
  713. ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE;
  714. }
  715. if(0U != (adc_interrupt & ADC_INT_EOC)){
  716. ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE;
  717. }
  718. if(0U != (adc_interrupt & ADC_INT_EOIC)){
  719. ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE;
  720. }
  721. }
  722. /*!
  723. \brief disable ADC interrupt
  724. \param[in] adc_periph: ADCx,x=0,1,2
  725. only one among these parameters can be selected
  726. \param[in] adc_interrupt: the adc interrupt flag
  727. one or more parameters can be selected
  728. \arg ADC_INT_WDE: analog watchdog interrupt flag
  729. \arg ADC_INT_EOC: end of group conversion interrupt flag
  730. \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag
  731. \param[out] none
  732. \retval none
  733. */
  734. void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt)
  735. {
  736. if(0U != (adc_interrupt & ADC_INT_WDE)){
  737. ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE;
  738. }
  739. if(0U != (adc_interrupt & ADC_INT_EOC)){
  740. ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE;
  741. }
  742. if(0U != (adc_interrupt & ADC_INT_EOIC)){
  743. ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE;
  744. }
  745. }
  746. /*!
  747. \brief configure ADC analog watchdog single channel
  748. \param[in] adc_periph: ADCx,x=0,1,2
  749. only one among these parameters can be selected
  750. \param[in] adc_channel: the selected ADC channel
  751. only one among these parameters can be selected
  752. \arg ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0)
  753. \param[out] none
  754. \retval none
  755. */
  756. void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel)
  757. {
  758. ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
  759. ADC_CTL0(adc_periph) |= (uint32_t)adc_channel;
  760. ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
  761. }
  762. /*!
  763. \brief configure ADC analog watchdog group channel
  764. \param[in] adc_periph: ADCx,x=0,1,2
  765. only one among these parameters can be selected
  766. \param[in] adc_channel_group: the channel group use analog watchdog
  767. only one parameter can be selected
  768. \arg ADC_REGULAR_CHANNEL: regular channel group
  769. \arg ADC_INSERTED_CHANNEL: inserted channel group
  770. \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group
  771. \param[out] none
  772. \retval none
  773. */
  774. void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group)
  775. {
  776. ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
  777. /* select the group */
  778. switch(adc_channel_group){
  779. case ADC_REGULAR_CHANNEL:
  780. ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN;
  781. break;
  782. case ADC_INSERTED_CHANNEL:
  783. ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN;
  784. break;
  785. case ADC_REGULAR_INSERTED_CHANNEL:
  786. ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN);
  787. break;
  788. default:
  789. break;
  790. }
  791. }
  792. /*!
  793. \brief disable ADC analog watchdog
  794. \param[in] adc_periph: ADCx,x=0,1,2
  795. only one among these parameters can be selected
  796. \param[out] none
  797. \retval none
  798. */
  799. void adc_watchdog_disable(uint32_t adc_periph)
  800. {
  801. ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
  802. }
  803. /*!
  804. \brief configure ADC analog watchdog threshold
  805. \param[in] adc_periph: ADCx,x=0,1,2
  806. only one among these parameters can be selected
  807. \param[in] low_threshold: analog watchdog low threshold,0..4095
  808. \param[in] high_threshold: analog watchdog high threshold,0..4095
  809. \param[out] none
  810. \retval none
  811. */
  812. void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold)
  813. {
  814. ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold);
  815. ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold);
  816. }
  817. /*!
  818. \brief configure ADC oversample mode
  819. \param[in] adc_periph: ADCx,x=0,1,2
  820. only one among these parameters can be selected
  821. \param[in] mode: ADC oversampling mode
  822. only oneparameter can be selected
  823. \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger
  824. \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger
  825. \param[in] shift: ADC oversampling shift
  826. only oneparameter can be selected
  827. \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift
  828. \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift
  829. \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift
  830. \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift
  831. \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift
  832. \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift
  833. \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift
  834. \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift
  835. \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift
  836. \param[in] ratio: ADC oversampling ratio
  837. only oneparameter can be selected
  838. \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2
  839. \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4
  840. \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8
  841. \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16
  842. \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32
  843. \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64
  844. \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128
  845. \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256
  846. \param[out] none
  847. \retval none
  848. */
  849. void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint8_t ratio)
  850. {
  851. if(ADC_OVERSAMPLING_ONE_CONVERT == mode){
  852. ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS;
  853. }else{
  854. ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS);
  855. }
  856. /* config the shift and ratio */
  857. ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS));
  858. ADC_OVSAMPCTL(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio);
  859. }
  860. /*!
  861. \brief enable ADC oversample mode
  862. \param[in] adc_periph: ADCx,x=0,1,2
  863. only one among these parameters can be selected
  864. \param[out] none
  865. \retval none
  866. */
  867. void adc_oversample_mode_enable(uint32_t adc_periph)
  868. {
  869. ADC_OVSAMPCTL(adc_periph) |= ADC_OVSAMPCTL_OVSEN;
  870. }
  871. /*!
  872. \brief disable ADC oversample mode
  873. \param[in] adc_periph: ADCx,x=0,1,2
  874. only one among these parameters can be selected
  875. \param[out] none
  876. \retval none
  877. */
  878. void adc_oversample_mode_disable(uint32_t adc_periph)
  879. {
  880. ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN);
  881. }